CS3865C
Operating Description: continued
Design Considerations
High frequency circuit layout techniques are imperative to
prevent pulse-width jitter. This is usually caused by exces-
sive noise pick-up imposed on the current sense and volt-
age feed-back inputs. Noise immunity can be improved by
lowering circuit impedances at these points. The printed
circuit board layout should contain a ground plane with
low current signal and high current switch and output
grounds returning on separate paths back to the input fil-
ter capacitor. Ceramic bypass capacitors (0.1µF) connected
directly to V
CC
and V
REF
may be required to improve noise
filtering. They provide a low impedance path for filtering
the high frequency noise. All high current loops should be
kept as short as possible using heavy copper runs. The
error amp compensation circuitry and the converter out-
put voltage-divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
Timing Diagram
SYNC
C
T
Latch 1
“Set” Input
COMP
1
Sense
1
Latch 1
“Reset” Input
V
OUT1
ENABLE
2
0V
Latch 2
“Set” Input
COMP
2
Sense
2
Latch 2
“Reset” Input
V
OUT2
Applications Diagram
Dual Boost Regulator
V
CC
CF1 +
5.0V
CF2
V
REF
2.5V
R
Sync
V
OUT
1
R
FB
1
R
FB
2
V
FB
1
COMP
1
ENABLE
2
V
OUT
2
R
FB
3
R
FB
4
V
FB
2
COMP
2
+
-
Error
Amp 2
R
T
+
Oscillator
Q1
PWM
Latch 1
S
Q
R
V
OUT1
R
Sense1
Sense
1
Q2
Current Sense
Comparator 1
2R
+
-
1.0mA
R
0.5V
PWM
Latch 2
S
RQ
R
V
OUT2
L2
D2
+
V
OUT
2
C
OUT
2
R
Internal
Bias
+
3.4V
-
20kΩ
+
Reference
Regulator
+
-
VIN
V
CC
+
UVLO -
+
-
17V
14V
L1
D1
V
OUT
1
C
OUT
1
V
REF
UVLO
C
T
Current Sense
2R Comparator 1
+
+
-
-
Error 1.0mA
R
+ 0.5V
Amp 1
250µA
+
Sense
2
R
Sense2
Gnd
Pwr Gnd
7
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
