CS3842B/3843B
Figure 3: Oscillator
cycle tends to exceed the maximum allowed, to prevent
transformer saturation in some power supplies, the inter-
nal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator timing
components.
V
OSC
OSC
RESET
EA Output
Switch
Current
V
CC
Setting the Oscillator
The oscillator timing capacitor, C
T
, is charged by V
REF
through R
T
and discharged by an internal current source
(Figure 3). During the discharge time, the internal clock
signal blanks out the output to the Low state, thus provid-
ing a user selected maximum duty cycle clamp.
Charge and discharge times are determined by the general
formulas:
t
c
= R
T
C
T
ln
I
OUT
V
OUT
(
V
REF
– V
lower
V
REF
– V
upper
)
)
Figure 2: Timing Diagram for key CS-384XB parameters
t
d
= R
T
C
T
ln
(
V
REF
– I
d
R
T
–V
lower
V
REF
– I
d
R
T
– V
upper
V
REF
R
T
OSC
C
T
Gnd
Substituting in typical values for the parameters in the
above formulas:
V
REF
= 5.0V, V
upper
= 2.7V, V
lower
= 1.0V, I
d
= 8.3mA,
t
c
≈
0.5534R
T
C
T
t
d
= R
T
C
T
ln
then
V
upper
(
2.3 – 0.0083 R
T
4.0 – 0.0083 R
T
)
V
lower
t
c
Sawtooth Mode
The frequency and maximum duty cycle can be deter-
mined from the Typical Performance Characteristics
graphs.
t
d
Grounding
LARGE R
T
(≈10kΩ)
V
OSC
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to ground in a single
point ground.
The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
Internal Clock
Triangular Mode
SMALL R
T
(≈700kΩ)
V
REF
Internal Clock
Figure 3: Oscillator Timing Network and parameters
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
