CS2842A/3843A SERIES
Circuit Description: continued
former saturation in some power supplies, the internal
oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator com-
ponents.
V
OSC
OSC
RESET
EA Output
Switch
Current
V
CC
Setting the Oscillator
Oscillator timing capacitor, C
T
, is charged by V
REF
through
R
T
and discharged by an internal current source. During
the discharge time, the internal clock signal blanks out the
output to the Low state, thus providing a user selected
maximum duty cycle clamp. Charge and discharge times
are determined by the formula:
I
OUT
V
OUT
t
c
= R
T
C
T
ln
(
V
REF
- V
lower
V
REF
- V
upper
)
)
Figure 2: Timing Diagram for key CS2841B parameters
t
d
= R
T
C
T
ln
(
V
REF
- I
d
R
T
- V
lower
V
REF
- I
d
R
T
- V
upper
V
REF
R
T
OSC
C
T
Gnd
Substituting in typical values for the parameters in the
above formulas:
V
REF
= 5.0V, V
upper
= 2.7V, V
lower
= 1.0V, I
d
= 8.3mA
t
c
≈
0.5534R
T
C
T
t
d
= R
T
C
T
ln
(
2.3 - 0.0083 R
T
4.0 - 0.0083 R
T
)
Timing parameters
V
upper
The frequency and maximum duty cycle can be deter-
mined using the Typical Performance Characteristic
graphs.
Grounding
V
lower
t
c
Sawtooth Mode
t
d
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd pin in a sin-
gle point ground.
The transistor and 5kΩ potentiometer, shown in the test
circuit, are used to sample the oscillator waveform and
apply an adjustable ramp to
Sense
.
LARGE R
T
(≈10kΩ)
V
OSC
Internal Clock
Triangular Mode
SMALL R
T
(≈700kΩ)
V
REF
Internal Clock
Figure 3: Oscillator Timing Network and parameters
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
