CTM8B54E/55E/56E/57E
EPROM-Based 8-Bit CMOS Microcontroller
8.2 Pad Assignment for CTM8B55E and CTM8B57E
20
17
19
18
16
15
Vss
PC6
PC5
PC4
PA0
PA1
Pad of CTM8B55E/57E
PA2
PA3
PC3
PC2
Chip size : 2201um x 1822um
Pad size : 110um x 110um
PB0
PC1
1
2
8
3
4
5
6
7
Pad No.
1
Pad
PB1
X
Y
Pad No.
14
Pad
PC6
X
Y
217.01
93.20
2117.01
1627.80
1738.75
1733.20
1733.20
2
3
4
5
PB2
PB3
PB4
PB5
476.09
720.67
979.75
93.20
93.20
93.20
93.20
15
16
17
18
PC7
OSCO
OSCI
1830.89
1595.29
1210.68
MCLR
1224.33
/Vpp
863.95
603.04
1738.79
1738.75
TOCKI/SCL
Vdd
6
7
PB6
PB7
1483.41
1727.99
93.20
93.20
19
20
344.41
101.98
93.21
93.21
93.21
93.21
93.21
1738.75
1644.97
1372.18
1127.60
868.52
623.94
364.86
Vss
8
PC0
PC1
1987.07
2117.01
2117.01
2117.01
2117.01
2117.01
93.20
21
22
23
24
25
26
9
361.40
620.48
865.06
1124.14
1386.72
PA0
PA1
10
11
12
13
PC2
PC3
PC4
PC5
PA2
PA3/SDA
PB0
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.1 Dec 26,2001
Tel:886-3-3529445
Page 22 of 23
Fax:886-3-3521052
CERAMATE [ CERAMATE TECHNICAL ]
