24LC02
2048-Bits Serial EEPROM with Write Protect
! #ꢀꢁꢀꢂꢃꢄꢅꢀꢆꢃꢇꢆꢁ
7*ꢀꢁ ꢂꢃꢂꢄ6
Thigh
Tf
Tr
Tlow
Tlow
SCL
Thd:Sta
Tsu:Dat
Tsu:Sta
Thd:Dat
Tsu:Sta
SDA
IN
Tbuf
Taa
Tdh
SDA
OUT
SDA
SCL
DATA
CHANGE
DATA STABLE
Figure 1. Data Validity
SDA
SCL
START
BIT
STOP
BIT
Figure 2. Definition of Start and Stop
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM
TRANSMITTER
DATA OUTPUT FROM
RECEIVER
ACKNOWLEDGE
START
Figure 3. Acknowledge Response from Receiver
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Dec. 26, 2001
Page 8 of 12
Fax:886-3-3521052