UPC2745TB, UPC2746TB
ELECTRICAL CHARACTERISTICS (TA = +25 °C, ZL = ZS = 50 Ω)
PART NUMBER
PACKAGE OUTLINE
UPC2745TB
S06
UPC2746TB
S06
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
RLIN
Input Return Loss, VCC = 3.0 V, f = 0.5 GHz
VCC = 3.0 V, f = 1 GHz
dB
dB
dB
dB
8
11
13
14
6.5
10
13
10
VCC = 3.0 V, f = 2 GHz
VCC = 1.8 V, f = 0.5 GHz
10
RLOUT
ISOL
Output Return Loss, VCC = 3.0 V, f = 0.5 GHz
VCC = 3.0 V, f = 1 GHz
dB
dB
dB
dB
2.5
33
5.5
6.5
8.5
6.0
5.5
40
8.5
8.5
VCC = 3.0 V, f = 2 GHz
VCC = 1.8 V, f = 0.5 GHz
9.5
Isolation, VCC = 3.0 V, f = 0.5 GHz
VCC = 3.0 V, f = 1 GHz
dB
dB
dB
dB
38
33
30
35
45
38
VCC = 3.0 V, f = 2 GHz
VCC = 1.8 V, f = 0.5 GHz
37
IM3
3rd Order Intermodulation Distortion
VCC = 3.0 V, POUT = -20 dBm, f1 = 500 MHz, f2 = 502 MHz
VCC = 3.0 V, POUT = -20 dBm, f1 = 1000 MHz, f2 = 1002 MHz
VCC = 1.8 V, POUT = -20 dBm, f1 = 500 MHz, f2 = 502 MHz
dBc
dBc
dBc
-54
-50
-31
-51
-37
ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C)
RECOMMENDED
OPERATING CONDITIONS
SYMBOLS
PARAMETERS
UNITS
RATINGS
SYMBOL
PARAMETER
UNITS MIN TYP MAX
VCC
Supply Voltage
V
4.0
(Pin 5, Pin 8)
VCC
TOP
Supply Voltage
V
2.7
3.0
3.3
PIN
Input Power
dBm
mW
°C
0
Operating Temperature
˚C
-40 +25 +85
PT
Total Power Dissipation2
Operating Temperature
Storage Temperature
200
TOP
-45 to +85
-55 to +150
TSTG
°C
Notes:
1. Operation in excess of any one of these parameters may result
in permanent damage.
2. Mounted on double sided copper clad 50 x 50 x 1.6 mm epoxy
glass PWB (TA = +85°C).
PIN DESCRIPTION
Pin
No.
Pin
Name
Applied
Voltage
(V)
Description
Internal Equivalent Circuit
1
Input
Signal input pin. An internal matching
circuit, configured with resistors, enables
50 Ω connection over a wide bandwidth.
This pin must be coupled to the signal source
with a blocking capacitor.
6
4
4
6
Output
Signal output pin. An internal matching
circuit, configured with resistors, enables
50 Ω connection over a wide bandwidth.
This pin must be coupled to the output
load with a blocking capacitor.
1
VCC
2.7 to 3.3
Power supply pin. This pin should be
externally equipped with a bypass capacitor
to minimize ground impedance.
2
3
5
2
3
5
GND
0
Ground pin. This pin should be connected
to system ground with minimum inductance.
Ground pattern on the board should be
formed as wide as possible. All the ground
pins must be connected together with wide
ground pattern to minimize impedance
difference.
CEL [ CALIFORNIA EASTERN LABS ]
