NEZ5964-15D
NEZ5964-15DL
NEZ5964-8D
NEZ5964-8DL
NEZ5964-4D
NEZ5964-4DL
C-BAND INTERNALLY
MATCHED POWER GaAs MESFET
FEATURES
OUTPUT POWER AND EFFICIENCY
vs. INPUT POWER
•
•
•
•
HIGH POUT
18W (42.5 dBm) Typ P1dB for NEZ5964-15D/15DL
100%
80%
45
40
35
-15D
-8D
9W (39.5 dBm) Typ P1dB for NEZ5964-8D/8DL
4.5W (36.5 dbm) Typ P1dB for NEZ5964-4D/4DL
POUT
HIGH EFFICIENCY
37% ηADD for 4.5W Device
35% ηADD for 9W Device
33% ηADD for 18W Device
-4D
60%
40%
-4D
LOW IMD
30
25
20
-8D
-15D
-45 dBc IM3 @ 31.5 dBm POUT (SCL) -15DL
-45 dBc IM3 @ 29 dBm POUT (SCL) -8DL
-45 dBc IM3 @ 26 dBm POUT (SCL) -4DL
20%
0%
Efficiency
32
SiO2 PASSIVATED CHIP
For Power/Gain Stability Under RF Overdrive
CLASS A OPERATION
•
•
•
•
17
12
37
22
27
INTERNALLY MATCHED (IN/OUT)
Input Power, PIN (dBm)
SUPERIOR GAIN FLATNESS
INDUSTRY COMPATIBLE HERMETIC PACKAGES
ELECTRICAL CHARACTERISTICS (TC = 25°C)
PART NUMBER
NEZ5964-4D
NEZ5964-4DL
T-61
NEZ5964-8D
NEZ5964-8DL
T-61
NEZ5964-15D
NEZ5964-15DL
T-65
PACKAGE OUTLINE
SYMBOLS PARAMETERS AND CONDITIONS
UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX TEST CONDITIONS
1
P1dB
Output Power at PIdB
IDSQ = 0.8A, (RF Off)
IDSQ = 1.6A
dBm 35.5 36.5
dBm
dBm
VDS = 10V
f = 5.9
to 6.45 GHz
38.5 39.5
IDSQ = 4.0A
41.5 42.5
33
ηADD Power Added Efficiency @ P1dB
%
A
37
1.1
35
Zs = ZL
IDS
GL
IM3
Drain Current at P1dB
Linear Gain
1.5
-42
3.5
2.2
3.0
4.4 6.0
9.0
50 ohms
dB
9.0 10.0
8.5
9.5
8.0
3rd Order Intermodulation Distortion3 at
VDS = I0V
-XDL Pout = 26 dBm SCL2, IDSQ = 0.5 x IDSS
Option Pout = 29 dBm SCL2, IDSQ = 0.5 x IDSS
dBc
dBc
-45
f1 = 6.44 GHz
f2 = 6.45 GHZ
2 Equal Tones
-45
4.5
-42
7.0
Only Pout = 31.5 dBm SCL2, IDSQ = 0.5 x IDSS dBc
-45 -42
9.2 14.0
IDSS
VP
Saturated Drain Current, VGS = 0 V
Pinch Off Voltage
IDS = 15 mA
A
1.0
2.3
2.0
4.0
V
V
V
-3.5 -2.0 -0.5
VDS = 2.5 V
IDS = 30 mA
IDS = 60 mA
-3.5 -2.0 -0.5
-3.5 -2.2 -0.5
BVDGO Drain - Gate Breakdown Voltage
IDG = 15 mA
V
V
V
20
22
IDG = 30 mA
IDG = 60 mA
20
22
20
22
gm
Transconductance
IDS = I A
mS
mS
mS
1300
5.0
IDS = 2 A
IDS = 4 A
2600
2.5
5200
1.3 1.5
RTH(CH-C) Thermal Resistance (Channel to Case) °C/W
∆T(CH-C) Channel Temperature Rise4
°C
Notes:
6.0
48
3.0
48
60
3. Maximum Spec Applies to -XDL Option Only.
4. ∆T(CH-C) = TCH - TC = 10 V x IDSQ x RTH (CH-C) MAX.
1. P1dB: Ouptut Power at the 1dB Gain Compression Point.
2. SCL: Single Carrier Level.
California Eastern Laboratories
CEL [ CALIFORNIA EASTERN LABS ]
