CAT28C64B
HARDWARE DATA PROTECTION
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
The following is a list of hardware data protection fea-
tures that are incorporated into the CAT28C64B.
SOFTWARE DATA PROTECTION
(1) VCC sense provides for write protection when VCC
falls below 3.5V min.
The CAT28C64B features a software controlled data
protectionschemewhich, onceenabled, requiresadata
algorithmtobeissuedtothedevicebeforeawritecanbe
performed. The device is shipped from Catalyst with the
softwareprotectionNOTENABLED(theCAT28C64Bis
in the standard operating mode).
(2) A power on delay mechanism, tINIT (see AC charac-
teristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
ADDRESS:
AA
WRITE DATA:
ADDRESS:
AA
1555
1555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
ADDRESS:
55
0AAA
0AAA
WRITE DATA:
ADDRESS:
A0
WRITE DATA:
ADDRESS:
80
1555
1555
WRITE DATA:
ADDRESS:
AA
SOFTWARE DATA
PROTECTION ACTIVATED
(1)
1555
WRITE DATA:
XX
WRITE DATA:
ADDRESS:
55
TO ANY ADDRESS
0AAA
WRITE LAST BYTE
TO
LAST ADDRESS
WRITE DATA:
ADDRESS:
20
1555
28C64B F12
5094 FHD F09
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
BLC
Doc. No. 25006-0A 2/98 P-1
10
CATALYST [ CATALYST SEMICONDUCTOR ]
