CAT1026, CAT1027
Immediate/Current Address Read
Sequential Read
The CAT1026 and CAT1027 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N + 1. For N = E = 255,
the counter will wrap around to zero and continue to
clock out valid data. After the CAT1026 and CAT1027
receive a slave address (with the R/W bit set t o one), an
acknowledge is issued, and the requested 8-bit byte is
transmitted. The master device does not send an
acknowledge, but will generate a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1026 and CAT1027 send the
inital 8-bit byte requested, the Master responds with an
acknowledge which tells the device it requires more
data.TheCAT1026andCAT1027willcontinuetooutput
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1026 and
CAT1027issentsequentiallywiththedatafromaddress
N followed by data from address N+1. The READ
operationaddresscounterincrementsalloftheCAT1026
and CAT1027 address bits so that the entire memory
array can be read during one operation.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
slave address and byte addresses of the location it
wishes to read. After the CAT1026 and CAT1027
acknowledge, the Master device sends the START
condition and the slave address again, this time with the
R/W bit set to one. The CAT1026 and CAT1027 then
respond with an acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Figure 12. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 13. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc No. 3010, Rev. K
13
CATALYST [ CATALYST SEMICONDUCTOR ]
