CAT1021, CAT1022, CAT1023
Acknowledge Polling
Preliminary Information
memory array is protected and becomes read only. The
CAT1021 will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issuedtoindicatetheendofthehost’swriteopration, the
CAT1021/22/23 initiates the internal write cycle. ACK
pollingcanbeinitiatedimmediately.Thisinvolvesissuing
the start condition followed by the slave address for a
write operation. If the device is still busy with the write
operation, no ACK will be returned. If a write operation
hascompleted, anACKwillbereturnedandthehostcan
then proceed with the next read or write operation.
Read Operations
The READ operation for the CAT1021/22/23 is initiated
in the same manner as the write operation with one
exception, the R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1021 only) allows the
user to protect against inadvertent memory array
programming. If the WP pin is tied to VCC, the entire
Figure 10. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc. No. 3009, Rev. E
12
CATALYST [ CATALYST SEMICONDUCTOR ]
