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CAT1021ZD4E-42TE13 参数 Datasheet PDF下载

CAT1021ZD4E-42TE13图片预览
型号: CAT1021ZD4E-42TE13
PDF下载: 下载PDF文件 查看货源
内容描述: 监控电路,带有I2C串行2K位CMOS EEPROM ,手动复位及看门狗定时器 [Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM, Manual Reset and Watchdog Timer]
分类和应用: 电源电路电源管理电路监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 20 页 / 149 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT1021, CAT1022, CAT1023  
ACKNOWLEDGE  
WRITE OPERATIONS  
After a successful data transfer, each receiving device  
is required to generate an acknowledge. The  
acknowledging device pulls down the SDA line during  
the ninth clock cycle, signaling that it received the 8 bits  
of data.  
Byte Write  
In the Byte Write mode, the Master device sends the  
STARTconditionandtheslaveaddressinformation(with  
theR/Wbitsettozero)totheSlavedevice.AftertheSlave  
generates an acknowledge, the Master sends a 8-bit  
address that is to be written into the address pointers of  
thedevice. Afterreceivinganotheracknowledgefromthe  
Slave, the Master device transmits the data to be written  
into the addressed memory location. The device  
acknowledges once more and the Master generates the  
STOP condition. At this time, the device begins an  
internalprogrammingcycletonon-volatilememory.While  
the cycle is in progress, the device will not respond to any  
request from the Master device.  
Alldevicesrespondwithanacknowledgeafterreceiving  
a START condition and its slave address. If the device  
has been selected along with a write operation, it  
responds with an acknowledge after receiving each 8-  
bit byte.  
When a device begins a READ mode it transmits 8 bits  
of data, releases the SDA line and monitors the line for  
anacknowledge.Onceitreceivesthisacknowledge,the  
device will continue to transmit data. If no acknowledge  
is sent by the Master, the device terminates data  
transmission and waits for a STOP condition.  
Figure 5. Start/Stop Timing  
SDA  
SCL  
START BIT  
STOP BIT  
Figure 6. Acknowledge Timing  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM TRANSMITTER  
DATA OUTPUT  
FROM RECEIVER  
START  
ACKNOWLEDGE  
Figure 7. Slave Address Bits  
Default Configuration  
1
0
1
0
0
0
0
R/W  
Doc. No. 3009, Rev. K  
10  
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