CAT1021, CAT1022, CAT1023
RESET CIRCUIT AC CHARACTERISTICS
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Units
tPURST
tRPD
Reset Timeout
Note 2
Note 3
130
200
270
5
ms
µs
VTH to RESET Output Delay
tGLITCH
MR Glitch
tMRW
VCC Glitch Reject Pulse Width
Manual Reset Glitch Immunity
MR Pulse Width
Note 4, 5
Note 1
Note 1
Note 1
30
ns
ns
µs
µs
100
5
tMRD
MR Input to RESET Output Delay
1
tWD
Watchdog Timeout
Note 1
1.0
1.6
2.3
sec
POWER-UP TIMING5,6
Test
Conditions
Symbol
Parameter
Min
Typ
Max
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
270
270
ms
ms
AC TEST CONDITIONS
Parameter
Test Conditions
0.2 VCC to 0.8 VCC
10 ns
Input Pulse Voltages
Input Rise and Fall times
Input Reference Voltages
Output Reference Voltages
0.3 VCC , 0.7 VCC
0.5 VCC
Current Source: IOL = 3 mA;
CL = 100 pF
Output Load
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Max
Units
(5)
NEND
Endurance
MIL-STD-883, Test Method 1033 1,000,000
Cycles/Byte
Years
(5)
TDR
Data Retention
ESD Susceptibility
Latch-Up
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
2000
100
(5)
VZAP
Volts
(5)(7)
ILTH
mA
Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
3. Power-Down, Input Reference Voltage V = V , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
CC
TH
4.
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. and t are the delays required from the time V is stable until the specified memory operation can be initiated.
V
Glitch Reference Voltage = V ; Based on characterization data
THmin
CC
t
PUR
PUW
CC
7. Latch-up protection is provided for stresses up to 100 mA on input and output pins from -1 V to V + 1 V.
CC
Doc. No. 3009, Rev. K
6
CATALYST [ CATALYST SEMICONDUCTOR ]
