Preliminary Information
CAT1021, CAT1022, CAT1023
Immediate/Current Address Read
Sequential Read
The CAT1021/22/23 address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
accessdatafromaddressN+1.Foralldevices,N=E=255.
The counter will wrap around to Zero and continue to
clock out valid data for the 2K devices. After the
CAT1021/22/23 receives its slave address information
(with the R/W bit set to one), it issues an acknowledge,
then transmits the 8-bit byte requested. The master
devicedoesnotsendanacknowledge, butwillgenerate
a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1021/22/23 sends the inital 8-
bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more
data.TheCAT1021/22/23willcontinuetooutputan8-bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1021/22/23 is
sent sequentially with the data from address N followed
bydatafromaddressN+1.TheREADoperationaddress
counter increments all of the CAT1021/22/23 address
bits so that the entire memory array can be read during
one operation.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’writeoperationbysendingtheSTARTcondition,
slave address and byte addresses of the location it
wishestoread.AftertheCAT1021/22/23acknowledges,
the Master device sends the START condition and the
slaveaddressagain,thistimewiththeR/Wbitsettoone.
TheCAT1021/22/23thenrespondswithitsacknowledge
and sends the 8-bit byte requested. The master device
does not send an acknowledge but will generate a
STOP condition.
Figure 11. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 12. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc No. 3009, Rev. E
13
CATALYST [ CATALYST SEMICONDUCTOR ]
