CAT1021, CAT1022, CAT1023
RESET CIRCUIT AC CHARACTERISTICS
Symbol
tPURST
tRDP
Parameter
Test Conditions
Note 2
Min
Typ
Max
270
5
Units
ms
µs
Power-Up Reset Timeout
VTH to RESET output Delay
VCC Glitch Reject Pulse Width
130
200
Note 3
tGLITCH
Note 4, 5
Note 1
30
ns
MR Glitch Manual Reset Glitch Immunity
100
ns
tMRW
tMRD
tWD
MR Pulse Width
Note 1
5
µs
MR Input to RESET Output Delay
Watchdog Timeout
Note 1
1
µs
Note 1
1.0
1.6
2.1
sec
POWER-UP TIMING (5), (6)
Symbol
tPUR
Parameter
Test Conditions
Min
Typ
Max
270
270
Units
ms
Power-Up to Read Operation
Power-Up to Write Operation
tPUW
ms
AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
Input Rise and Fall times
Input Reference Voltages
Output Reference Voltages
Output Load
0.2VCC to 0.8VCC
10ns
0.3VCC , 0.7VCC
0.5VCC
Current Source: IOL = 3mA; CL = 100pF
RELIABILITY CHARACTERISTICS
Symbol Parameter
Reference Test Method
Min
Max
Units
(5)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1,000,000
100
Cycles/Byte
Years
(5)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(5)
VZAP
2000
Volts
(5)(7)
ILTH
100
mA
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data
(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(6) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V.
Doc. No. 3009 Rev. L
6
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice