CAT25C128/256
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) — — — —
A.C. CHARACTERISTICS (CAT25C128)
Limits
Vcc=
VCC
=
VCC
=
1.8V-6.0V
2.5V-6.0V
4.5V-5.5V
Test
SYMBOL PARAMETER
Min.
Max.
Min.
70
Max.
Min.
Max.
UNITS
ns
Conditions
tSU
tH
Data Setup Time
Data Hold Time
100
100
250
250
DC
35
35
80
80
DC
70
ns
tWH
tWL
fSCK
tLZ
SCK High Time
150
150
DC
ns
SCK Low Time
ns
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
3
50
2
5
50
2
MHz
ns
(1)
tRI
µs
(1)
tFI
Input Fall Time
2
2
2
µs
CL = 50pF
tHD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
250
250
250
250
40
40
ns
tCD
ns
tWC
tV
10
10
5
ms
ns
250
250
80
tHO
0
0
0
ns
tDIS
tHZ
250
150
250
150
100
50
ns
ns
tCS
1000
1000
1000
50
250
250
250
50
100
100
100
50
ns
tCSS
tCSH
tWPS
tWPH
NOTE:
CS Setup Time
ns
CS Hold Time
ns
WP Setup Time
ns
WP Hold Time
50
50
50
ns
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25088-00 1/01
3
CATALYST [ CATALYST SEMICONDUCTOR ]
