PRELIMINARY
CALIFORNIA MICRO DEVICES
Pin Descriptions
V
IN
(pin 2) is the input power source for the device. Since
the charge pump draws current in pulses at the 250kHz
internal clock frequency, a low-ESR input decoupling
capacitor is usually required close to this pin to ensure
low noise operation.
CP+
and
CP-
(pins 9, 10) are used to connect the
external “flying” capacitor C
P
to the charge pump. The
charge stored in C
P
is transferred to the reservoir
capacitor C
S
at the 250kHz internal clock rate.
CS
(pin 3) is the output of the charge pump and is
connected to the external reservoir capacitor Cs. This
should be a low-ESR capacitor.
When the voltage on this pin reaches about 5.8V then
the charge pump pauses until the voltage on this pin
drops to about 5.7V. This gives rise to at least 100mV of
‘ripple’ (the frequency and amplitude of this ripple
depends upon values of Cp and Cs and also the ESR of
Cs).
Note that current may be drawn from this pin for other
applications (for example an additional, independent, 5V
LDO) as long as the total current is less than 100mA
(otherwise the part may overheat).
DGND
(pin 1) is the ground for the charge pump circuit.
This should be connected to the system (noisy) ground.
GND
(pin 4) is the ground reference for all internal circuits
except the charge pump. This pin should be connected to
a “clean” low-noise analog ground.
CM3702
EN_LDO, EN_Chip
(pins 6, 7) are active-high TTL-level
logic inputs to enable the linear regulator and charge
pump according to the following truth table:
EN_Chip EN_LDO CHARGE
REGULATOR
Pin 7
Pin 6
PUMP
1
1
Enabled
Enabled
1
0
Enabled
Disabled
0
1
Disabled
Disabled
0
0
Disabled
Disabled
When the LDO Regulator is disabled, an internal pull-
down with a nominal resistance of 500Ω is activated to
discharge the 5V output rail to ground.
When the charge pump is disabled or paused, the
internal 250kHz oscillator is disabled. The “flying
capacitor” C
P
will then stay connected between V_IN
and DGND, and C
S
will stay connected to the input of
the LDO regulator. In this mode, C
S
will discharge at a
rate determined by the input current of the LDO regulator.
BYP
(pin 5) is connected to the internal voltage reference
of the LDO regulator. An external bypass capacitor C
BYP
of 0.1uF is recommended to minimize internal voltage
reference noise and maximize power supply ripple
rejection.
V
OUT
(pin 8) is the regulated output. An output capacitor
may be added to improve noise and load-transient
response. When the LDO regulator is disabled, an internal
pull-down is activated to discharge the V
OUT
rail to GND.
Pinout Diagrams
Typical Application Circuit
© 2004 California Micro Devices Corp. All rights reserved
09/22/04
430 N. McCarthy Blvd, #100, Milpitas, California 95035
Tel: (408) 263-3214 Fax: (408) 263-7846
www.calmicro.com
2
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
