PRELIMINARY
CM3121
Dual Linear Voltage Regulator for DDR-I and DDR-II Memory
Features
•
•
•
•
Fully integrated power solution for DDR memory
ICs
Ideal for DDR-I (2.5V
DDQ
) and DDR-II (1.8V
DDQ
)
Lowest system cost and smallest footprint with just
two external output capacitors
Two linear regulators:
- V
DDQ
regulator with a maximum output current
of 1.5A shared by DRAM and V
TT
regulator
- source-sink V
TT
regulator with maximum out-
put current of 0.5A (DDR-I) or 0.3A (DDR-II)
Fault output indicates overcurrent condition in
either regulator, under voltage lock-out and over-
temperature condition
Reverse current protection if host is powered off
PSOP-8 package with integrated heat spreader
Lead-free versions available
Product Description
The CM3121 provides an integrated power solution for
DDR-I and DDR-II memory systems in consumer electron-
ics applications. The CM3121 is ideal for a 2.8V to 3.6V
supply for DDR-I memory and 2.2V to 2.8V for DDR-II mem-
ory. The CM3121 features two independent linear regula-
tors for V
DDQ
and V
TT
supply regulation. The default
voltage for V
DDQ
is 2.5V. The V
DDQ
regulator SENSE pin
allows for setting V
DDQ
in the 2.2V to 2.8V range, or DDR-II
memories from 1.7V to 1.9V. The V
TT
regulator output is
always half the V
DDQ
voltage, derived internally. A capacitor
should be connected to each of the two outputs.
When EN_DDR is set high, the two DDR regulators are dis-
abled to minimize overall system power dissipation such as
when memory is in standby.
The FAULT pin goes low whenever either of the two regula-
tors goes into current limit mode, the input voltage drops too
far or if overtemp occurs.
•
•
•
•
Applications
•
DDR-I and DDR-II memory power for:
−
Set Top Boxes, DVD Players, Games
−
Digital TVs, Flat Panel Displays
−
Printers, Digital Projectors
−
Embedded systems
−
Communications systems
The CM3121 is available in a PSOP-8 package that has
excellent thermal dissipation.
It is available with optional
lead-free finishing.
.
Typical Application Circuit
2.8V to 3.3V
Circuit Schematic
V
CC
V
DDQ
REGULATOR
V
DDQ
SENSE
V
DDQ
V
CC
V
DDQ
REGULATOR
V
DDQ
SENSE
V
DDQ
V
REF
V
DDQ
= 2.5V
C
CC
V
REF
V
DDQ
SENSE_ V
DDQ
Enable DDR
Memory #
EN_DDR
C
DDQ
EN_DDR
DDR
MEMORY
R
R
V
TT
REGULATOR
V
TT
R
V
TT
=1.25V
V
TT
REGULATOR
V
TT
R
VTT
SENSE_V
TT
SENSE V
TT
C
TT
SENSE V
TT
CURRENT LIMIT
OVERTEMP
LOW INPUT
FAULT
CPU
CORE
+ I/O
CURRENT LIMIT
OVERTEMP
LOW INPUT
FAULT
GND
GND
©
2004 California Micro Devices Corp. All rights reserved.
11/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
1
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
