欢迎访问ic37.com |
会员登录 免费注册
发布采购

CM3109-00SB 参数 Datasheet PDF下载

CM3109-00SB图片预览
型号: CM3109-00SB
PDF下载: 下载PDF文件 查看货源
内容描述: 2A吸入/源调节器的前端总线和DDR存储器总线终端 [2A Sink/Source Regulator for Front Side Bus and DDR Memory Bus Termination]
分类和应用: 总线通信调节器驱动程序和接口存储接口集成电路光电二极管双倍数据速率
文件页数/大小: 12 页 / 543 K
品牌: CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
 浏览型号CM3109-00SB的Datasheet PDF文件第4页浏览型号CM3109-00SB的Datasheet PDF文件第5页浏览型号CM3109-00SB的Datasheet PDF文件第6页浏览型号CM3109-00SB的Datasheet PDF文件第7页浏览型号CM3109-00SB的Datasheet PDF文件第8页浏览型号CM3109-00SB的Datasheet PDF文件第9页浏览型号CM3109-00SB的Datasheet PDF文件第10页浏览型号CM3109-00SB的Datasheet PDF文件第12页  
CM3109  
Application Information (cont’d)  
VCC  
VDDQ  
CVDDQ  
47uF  
VDDQ  
VCC  
VDDQSEL  
VTT  
CVCC  
47uF  
VDDQSEL  
BOOTSEL  
VSENSE  
GND  
FSBSEL  
SD  
GMCHVCCP  
RVDDQSEL  
4.7K  
CVTT  
FSBSEL  
0.1uF  
220uF  
GMCH_EN  
Figure 18. Typical Front Side Bus with Suspend to RAM Application Circuit  
shutdown periods. The V SEL input ensures that  
DDQ  
The above diagram shows the CM3109 connected to  
the CM3109 is in Front Side Bus mode, and the BOOT-  
SEL from the GMCH ensures the right Microprocessor  
the Intel 865 GMCH Front Side Bus V pin GMCH-  
TT  
VCCP. The Enable signal GMCH_EN is used to shut  
down the output of the CM3109 to save power during  
V
voltage is applied.  
TT  
V
DDQSEL  
FSBSEL  
VTT  
NOTE  
VCC (CPU Core)  
GMCH_EN  
"1"  
Don’t Care  
VDDQSEL/2  
(see note 1)  
For DDR  
Open or "0"  
Open or "0"  
"0"  
"1"  
1.225V  
1.45V  
For FSB  
For FSB  
Note 1:Assumes VDDQ and VDDQSEL are tied  
together in DDR application.  
GMCHVCCP  
Figure 19. Front Side Bus Timing diagram  
Table 1: V Output Selection Truth Table.  
TT  
© 2004 California Micro Devices Corp. All rights reserved.  
01/15/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214  
Fax: 408.263.7846  
www.calmicro.com  
11