PRELIMINARY
CM20LT-C
Backdrive Protection and Isolation
Backdrive current is defined as the undesirable current
flow through an I/O pin when that I/O pin’s voltage
exceeds the related local supply voltage for that cir-
cuitry. This is a potentially common occurrence in mul-
timedia
entertainment
systems
with
multiple
components and several power plane domains in each
system.
For example, if a DVD player is switched off and an
HDMI connected TV is powered on, there is a possibil-
ity of reverse current flow back into the main power
supply rail of the DVD player from pull-ups in the TV.
As little as a few milliamps of backdrive current flowing
back into the power rail can charge the DVD player’s
bulk bypass capacitance on the power rail to some
intermediate level. If this level rises above the power-
on-reset (POR) voltage level of some of the integrated
circuits in the DVD player, then these devices may not
reset properly when the DVD player is turned back on.
If any SOC devices are incorporated in the design
which have built-in level shifter and/or ESD protection
structures, there can be a risk of permanent damage
due to backdrive. In this case, backdrive current can
forward bias the on-chip ESD protection structure. If
the current flow is high enough, even as little as a few
milliamps, it could destroy one of the SOC chip's inter-
nal DRC diodes, as they are not designed for passing
DC.
To avoid either of these situations, the CM20LT-C was
designed to block backdrive current, guaranteeing less
than 5µA into any I/O pin when the I/O pin voltage
exceeds its related operating CM20LT-C supply volt-
age.
+5V
LV_SUPPLY
=OFF
LOW VOLTAGE
HDMI ASIC
ASIC
HDMI SOURCE
HDMI SINK
Figure 1. Backdrive Protection Diagram.
Display Data Channel (DDC) lines
The DDC interface is based on the I
2
C serial bus proto-
col for EDID configuration.
DYNAMIC PULLUPS
Based on the HDMI specification, the maximum capac-
itance of the DDC line can approach 800pF (50pF from
source, 50pF from sink, and 700pF from cable). At the
upper range of capacitance values (i.e. long cables), it
becomes impossible for the DDC lines to meet the I
2
C
timing specifications with the minimum pull-up resistor
of 1.5k
Ω
.
© 2005, 2006California Micro Devices Corp. All rights reserved.
4/3/2006
For this reason, the CM20LT-C was designed with an
internal I
2
C accelerator to meet the AC timing specifi-
cation even with very long and non-compliant cables.
The internal accelerator increases the positive slew
rate of the DDC_CLK_OUT and DDC_DAT_OUT lines
whenever the sensed voltage level exceeds 0.3*VIN_2
(approximately 1.5V). This provides faster overall rise-
time in heavily loaded situations without overloading
the mutli-drop open drain I
2
C outputs elsewhere.
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
-
Tel: 408.263.3214
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Fax: 408.263.7846
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www.calmicro.com
3
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
