PRELIMINARY
CM20LT
PACKAGE / PINOUT DIAGRAM
TOP VIEW
VIN_1
DDC_CLK_IN
DDC_DAT_IN
VIN_2
1
2
3
4
8
7
6
5
DDC_CLK_OUT
DDC_DAT_OUT
GND
VOUT
8-PIN MSOP/SOIC PACKAGE
Note: This drawing is not to scale.
PIN DESCRIPTIONS
PINS
1
NAME
VIN_1
ESD Level
2kV
4
DESCRIPTION
System Side Voltage Supply. This pin provides power to VOUT when
VIN_2 is "off". VIN_1 also enables/disables backdrive isolation pro-
tection on the DDC lines when VIN_1 is "off."
Cable Side Voltage Supply. This pin provides power to VOUT when
VIN_1 is "off". VIN_2 also provides ESD bias on the 8kV DDC_OUT
lines.
Bi-directional System Side (VIN_1 referenced logic level). Includes
CMOS low-level shifter for guaranteed local V
OL
.
Bi-directional Cable Side (VIN_2 referenced logic level ) plus 3.5pF
ESD. Includes Long Cable accelerator/driver. Connect to HDMI Pin
15.
Bi-directional System Side (VIN_1 referenced logic level). Includes
CMOS low-level shifter for guaranteed local V
OL
.
Bi-directional Cable Side (VIN_2 referenced logic level ) plus 3.5pF
ESD. Includes Long Cable accelerator/driver. Connect to HDMI Pin
16.
55mA minimum overcurrent protected 5V output.This output must be
bypassed with a 0.1µF ceramic capacitor. For Source, connect this
to HDMI Pin
GND reference.
4
VIN_2
8kV
3
2
8
DDC_CLK_IN
DDC_CLK_OUT
2kV
4
8kV
3
3
7
DDC_DAT_IN
DDC_DAT_OUT
2kV
4
8kV
3
5
VOUT
8kV
3
6
GND / TMDS_GND
N/A
Note 1: These 2 pins need to be connected together in-line on the PCB. See recommended layout diagram.
Note 2: This output can be connected to an external 0.1
µ
F ceramic capacitor/pads to mainatain backward compatibility with the
CM2020.
Note 3: Standard IEC 61000-4-2, C
DISCHARGE
=150pF, R
DISCHARGE
=330
Ω
, VIN_2 and VIN_1 within recommended operating con-
ditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1
µ
F ceramic capacitor
connected to GND.
Note 4: Human Body Model per MIL-STD-883, Method 3015, C
DISCHARGE
=100pF, R
DISCHARGE
=1.5k
Ω
, VIN_2and VIN_1 within
recommended operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a
0.1
µ
F ceramic capacitor connected to GND.
Note 5: These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at the
connector
© 2006 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
-
Tel: 408.263.3214
-
Fax: 408.263.7846
-
www.calmicro.com
4/18/2006
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
