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CM1215-02ST 参数 Datasheet PDF下载

CM1215-02ST图片预览
型号: CM1215-02ST
PDF下载: 下载PDF文件 查看货源
内容描述: 1,2和4通道低电容ESD阵列 [1-, 2- and 4-Channel Low Capacitance ESD Arrays]
分类和应用:
文件页数/大小: 10 页 / 339 K
品牌: CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
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PRELIMINARY  
CM1215  
APPLICATION INFORMATION  
Design Considerations  
In order to realize the maximum protection against  
ESD pulses, care must be taken in the PCB layout to  
minimize parasitic series inductances on the Supply/  
Ground rails as well as the signal trace segment  
between the signal input (typically a connector) and the  
ESD protection device. Refer to Figure 1, which illus-  
trates an example of a positive ESD pulse striking an  
input channel. The parasitic series inductance back to  
the power supply is represented by L1 and L2. The  
voltage VCL on the line being protected is:  
Similarly for negative ESD pulses, parasitic series  
inductance from the V pin to the ground rail will lead  
N
to drastically increased negative voltage on the line  
being protected.  
As a general rule, the ESD Protection Array should be  
located as close as possible to the point of entry of  
expected electrostatic discharges. The power supply  
bypass capacitor mentioned above should be as close  
to the V pin of the Protection Array as possible, with  
P
minimum PCB trace lengths to the power supply,  
ground planes and between the signal input and the  
ESD device to minimize stray series inductance.  
V
= Fwd voltage drop of D + V  
+
SUPPLY  
CL  
1
L1 x d(I  
) / dt+ L2 x d(IESD) / dt  
ESD  
where IESD is the ESD current pulse, and VSUPPLY  
is the positive supply voltage.  
Additional Information  
See also California Micro Devices Application Note  
AP-209, “Design Considerations for ESD Protection”,  
in the Applications section at www.calmicro.com.  
An ESD current pulse can rise from zero to its peak  
value in a very short time. As an example, a level 4  
contact discharge per the IEC61000-4-2 standard  
results in a current pulse that rises from zero to 30  
Amps in 1ns. Here d(IESD)/dt can be approximated by  
d(  
)/dt, or 30/(1x10-9). So just 10nH of series induc-  
ESD  
tance (L1 and L2 combined) will lead to a 300V incre-  
ment in VCL!  
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground  
© 2005 California Micro Devices Corp. All rights reserved.  
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112  
Tel: 408.263.3214  
Fax: 408.263.7846  
www.calmicro.com  
06/30/05  
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