CM1213
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 3, which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
inductance L on V
by clamping V at the break-
CL P
2
down voltage of the Zener diode. However, for the low-
est possible V , especially when V is biased at a
CL
P
voltage significantly below the Zener breakdown volt-
age, it is recommended that a 0.22μF ceramic chip
capacitor be connected between V and the ground
P
plane.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
the power supply is represented by L and L . The volt-
1
2
age V on the line being protected is:
CL
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt
+ L2 x d(IESD ) / dt
to the V pin of the Protection Array as possible, with
P
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
where I
the positive supply voltage.
is the ESD current pulse, and V
is
ESD
SUPPLY
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Additional Information
See also California Micro Devices Application Note
AP209, “Design Considerations for ESD Protection”, in
the Applications section at www.calmicro.com.
Amps in 1ns. Here d(I
)/dt can be approximated by
ESD
-9
ΔI
/Δt, or 30/(1x10 ). So just 10nH of series induc-
ESD
tance (L and L combined) will lead to a 300V incre-
1
2
ment in V
!
CL
Similarly for negative ESD pulses, parasitic series
inductance from the V pin to the ground rail will lead
N
to drastically increased negative voltage on the line
being protected.
The CM1213 has an integrated Zener diode between
V and V . This greatly reduces the effect of supply rail
P
N
L2
VCC
POSITIVE SUPPLY RAIL
VP
PATH OF ESD CURRENT PULSE I
ESD
L1
LINE BEING
PROTECTED
D1
D2
SYSTEM OR
CIRCUITRY
BEING
0.22μF
ONE
CHANNEL
OF
CHANNEL
INPUT
PROTECTED
25A
VCL
CM1213
0A
GROUND RAIL
VN
CHASSIS GROUND
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
© 2006 California Micro Devices Corp. All rights reserved.
03/02/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.cmd.com
7
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
