CM1210
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 3, which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
a R
of 1 ohm would result in a 10V increment in
OUT
V
for a peak I
of 10A.
CL
ESD
If the inductances and resistance described above are
close to zero, the rail-clamp ESD protection diodes will
do a good job of protection. However, since this is not
possible in practical situations, a bypass capacitor
must be used to absorb the very high frequency ESD
energy. So for any brand of rail-clamp ESD protection
diodes, a bypass capacitor should be connected
the power supply is represented by L and L . The volt-
1
2
age V on the line being protected is:
CL
between the V pin of the diodes and the ground plane
P
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt
+ L2 x d(IESD ) / dt
(V pin of the diodes) as shown in the Application Cir-
N
cuit diagram below. A value of 0.22µF is adequate.
Ceramic chip capacitors mounted with short printed
circuit board traces are good choices for this applica-
tion. Electrolytic capacitors should be avoided as they
have poor high frequency characteristics. For extra
protection, connect a zener diode in parallel with the
bypass capacitor to mitigate the effects of the parasitic
series inductance inherent in the capacitor. The break-
down voltage of the zener diode should be slightly
higher than the maximum supply voltage.
where I
is the ESD current pulse, and V
is
SUPPLY
ESD
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(I
)/dt can be approximated by
ESD
-9
∆I
/∆t, or 30/(1x10 ). So just 910nH of series induc-
ESD
tance (L and L combined) will lead to a 300V incre-
1
2
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
ment in V
!
CL
Similarly for negative ESD pulses, parasitic series
inductance from the V pin to the ground rail will lead
N
to drastically increased negative voltage on the line
being protected.
to the V pin of the Protection Array as possible, with
P
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Another consideration is the output impedance of the
power supply for fast transient currents. Most power
supplies exhibit a much higher output impedance to
Additional Information
fast transient current spikes. In the V
equation
CL
See also California Micro Devices Application Notes
AP209, “Design Considerations for ESD Protection”
and APxxx, "ESD Protection for USB 2.0 Systems".
above, the V
term, in reality, is given by (V
+
SUPPLY
DC
I
x R
), where V
and R
are the nominal
ESD
OUT
DC
OUT
supply DC output voltage and effective output imped-
ance of the power supply respectively. As an example,
L2
POSITIVE SUPPLY RAIL
VP
PATH OF ESD CURRENT PULSE I
ESD
D1
L1
LINE BEING
PROTECTED
SYSTEM OR
CIRCUITRY
BEING
0.22µF
ONE
CHANNEL
OF
CHANNEL
INPUT
PROTECTED
D2
20A
CM1210
VCL
0A
GROUND RAIL
VN
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
© 2004 California Micro Devices Corp. All rights reserved.
01/14/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
7
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
