CM1208-07/08
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to
Figure 1,
which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
the power supply is represented by L
1
and L
2
. The volt-
age V
CL
on the line being protected is:
V
CL
= Fwd voltage drop of D
1
+ V
SUPPLY
+ L
1
x d(I
ESD
)
/
dt
+ L
2
x d(I
ESD
)
/
dt
ance of the power supply respectively. As an example,
a R
OUT
of 1 ohm would result in a 10V increment in
V
CL
for a peak I
ESD
of 10A.
To mitigate these effects, a high frequency bypass
capacitor should be connected between the V
P
pin of
the ESD Protection Array and the ground plane. The
value of this bypass capacitor should be chosen such
that it will absorb the charge transferred by the ESD
pulse with minimal change in V
P
. Typically a value in
the 0.1µF to 0.2µF range is adequate for IEC-61000-4-
2 level 4 contact discharge protection (8kV). For higher
ESD voltages, the bypass capacitor should be
increased accordingly. Ceramic chip capacitors
mounted with short printed circuit board traces are
good choices for this application. Electrolytic capaci-
tors should be avoided as they have poor high fre-
quency characteristics. For extra protection, connect a
zener diode in parallel with the bypass capacitor to mit-
igate the effects of the parasitic series inductance
inherent in the capacitor. The breakdown voltage of the
zener diode should be slightly higher than the maxi-
mum supply voltage.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the V
P
pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
where I
ESD
is the ESD current pulse, and V
SUPPLY
is
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(I
ESD
)/dt can be approximated by
∆I
ESD
/∆t, or 30/(1x10
-9
). So just 10nH of series induc-
tance (L
1
and L
2
combined) will lead to a 300V incre-
ment in V
CL
!
Similarly for negative ESD pulses, parasitic series
inductance from the V
N
pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
Another consideration is the output impedance of the
power supply for fast transient currents. Most power
supplies exhibit a much higher output impedance to
fast transient current spikes. In the V
CL
equation
above, the V
SUPPLY
term, in reality, is given by (V
DC
+
I
ESD
x R
OUT
), where V
DC
and R
OUT
are the nominal
supply DC output voltage and effective output imped-
L
2
V
P
Additional Information
See also California Micro Devices Application Note
AP209, “Design Considerations for ESD Protection.”
POSITIVE SUPPLY RAIL
PATH OF ESD CURRENT PULSE I
ESD
D
1
ONE
CHANNEL
OF
CM1208
L
1
CHANNEL
INPUT
20A
LINE BEING
PROTECTED
D
2
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
V
CL
GROUND RAIL
0A
V
N
CHASSIS GROUND
Figure 1. Application of Positive ESD Pulse between Input Channel and Ground
©
2004 California Micro Devices Corp. All rights reserved.
02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
5
CALMIRCO [ CALIFORNIA MICRO DEVICES CORP ]
