TMC2490A
PRODUCT SPECIFICATION
1464
1472
1592
1600
1727
1715
0
0
625-line
525-line
PXCK
C
Y
C
Y
C
Y
C
Y
C
Y
C
C
Y
C
Y
C
C
Y
PD
7-0
C
Y
C
Y
C
B2
B732
732
R732
733
B734
734
R734
735
B736
736
R736 B800
800
R800
801
B801 R856
857
B0
0
R0
1
CBSEL
HYSNC
65-2490A-03
HDEL = 00
HDEL = 01
HDEL = 10
HDEL = 11
Figure 2a. HDEL TIming
1430
1435
1440
1440
1464
1472
1724
1712
1727
1715
0
0
17
3
625-line
525-line
PXCK
t
t
HP
SP
PD
7-0
FF
00
EAV
00
FV
FF
00
00
FV
C
Y
0
1
0
B0
t
SAV
DO
t
HS
HSYNC (Output)
HDEL = 2
t
t
DO
DO
PDC
65-2490A-04
Figure 2b. CCIR-656 Horizontal Interval Timing Detail
1430
1435
1440
1440
1464
1472
1727
1715
0
0
17
3
625-line
525-line
PXCK
t
t
S
H
Y
PD
C
B0
7-0
0
t
DO
t
HS
HSYNC (Output)
HDEL = 2
t
t
DO
DO
PDC
65-2490A-05
Figure 3. Master Mode Horizontal Interval Timing Detail
In CCIR-656 slave mode, it likewise holds each end-of-line
blank state until it receives the next end of active video
(EAV) signal embedded in the incoming data stream.
Horizontal and Vertical Timing
Horizontal and vertical video timing in the TMC2490A is
preprogrammed for line-locked systems with a 2x pixel
clock of 27.0 MHz.
The vertical field group comprises several different line
types based upon the Horizontal line time.
Table 3 and Table 4 show timing parameters for NTSC and
PAL standards and the resulting TMC2490A analog output
timing. The user provides exactly 720 pixels of active video
per line. In master mode, the TMC2490A precisely controls
the duration and activity of every segment of the horizontal
line and vertical field group. In external sync slave mode, it
holds the end-of-line blank state (e.g. front porch for active
video lines) until it receives the next horizontal sync signal.
H
= (2 x SL) + (2 x SH) [Vertical sync pulses]
= (2 x EL) + (2 x EH) [Equalization pulses]
SMPTE 170M NTSC and Report 624 PAL video standards
call for specific rise and fall times on critical portions of the
video waveform. The chip does this automatically, requiring
no user intervention. The TMC2490A digitally defines
12
REV. 1.0.2 2/27/02