PRODUCT SPECIFICATION
TMC2242A/TMC2242B
Description
(continued)
The filter response is flat to within
±
0.01 dB from 0.00 to
0.22 x f
s
, with stopband attenuation greater than 59.4 dB
from 0.28 x f
s
to the Nyquist frequency. The response is 6 dB
down at 0.25 x f
s
. Symmetric-coefficient filters such as the
TMC2242A and TMC2242B have linear phase response.
Full compliance with the CCIR-601 standard of 12 dB atten-
uation at 0.25 x f
s
is achieved by cascading two parts.
The TMC2242A and TMC2242B are fabricated on an
advanced submicron CMOS process. They are available in a
44-lead J-lead PLCC package. Performance is guaranteed
from 0
°
C to 70
°
C.
To perform decimation, the chip sets the output register
clock rate to half of the input rate. One output is then
obtained for every two inputs.
For interpolation, the user should bring SYNC HIGH for at
least one clock cycle, returning it LOW with the first desired
input data value. When interpolating, the chip will then con-
tinue to accept a new data input on each alternate rising edge
of the clock. When decimating, the chip will present one out-
put value for every two clock cycles. The user may leave
SYNC LOW or toggle it once per rising clock edge, with
equivalent performance.
The output data format is two's complement if TCO is
HIGH, inverted offset binary if LOW. The user can tailor the
output data word width to his/her system requirements using
the Rounding control. As shown in Table 4, the output is
half-LSB rounded to the resolution selected by the value of
RND
2-0
. The asynchronous three-state output enable control
simplifies connection to a data bus with other drivers.
Functional Description
The TMC2242A and TMC2242B implement a fixed-coeffi-
cient linear-phase Finite Impulse Response (FIR) filter of 55
effective taps, with special rate-matching input and output
structures to facilitate 2:1 decimation and 1:2 interpolation.
The faster of either the input or output registers will operate
at the guaranteed maximum clock rate (speed grade). The
total internal pipeline latency from the input of an impulse to
the corresponding output peak (digital group delay) is 34
cycles; the 55-value output response begins after 7 clock
cycles and ends after 61 cycles.
To perform interpolation, the chip slows the effective input
register clock rate to half the output rate. It internally inserts
zeroes between the incoming data samples to "pad" the input
data rate to match the output rate.
Table 1. Operating Modes
DEC
0
0
1
1
INT
0
1
0
1
TMC2242A
Equal Rate
Decimate
Equal Rate
TMC2242B
Interpolate (0 dB)
Decimate
Equal Rate
Interpolate (-6 dB) Interpolate (-6 dB)
1
Note:
1. With 15-bit overflow protection. All other modes on both
parts limit to 16 bits.
Pin Assignments
SO
13
SO
14
SO
15
OE
TCO
DEC
INT
SYNC
CLK
GND
SI
11
SO
13
SO
14
SO
15
OE
TCO
DEC
INT
SYNC
CLK
GND
SI
11
44
43
42
41
40
39
38
37
36
35
44
43
42
41
40
6
5
4
3
2
1
18
19
20
21
22
23
24
25
26
27
28
SO
12
SO
11
SO
10
SO
9
SO
8
GND
V
DD
SO
7
SO
6
SO
5
SO
4
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
TMC2242A
TMC2242B
GND
V
DD
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
V
DD
12
13
14
15
16
17
18
19
20
21
SO
3
SO
2
SO
1
SO
0
RND
2
RND
1
RND
0
SI
0
SI
1
SI
2
GND
65-2242A-02
65-2242A-02
44 Lead PLCC
2
SO
3
SO
2
SO
1
SO
0
RND
2
RND
1
RND
0
SI
0
SI
1
SI
2
GND
44 Lead MQFP
22
SO
12
SO
11
SO
10
SO
9
SO
8
GND
V
DD
SO
7
SO
6
SO
5
SO
4
34
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
TMC2242A
TMC2242B
GND
V
DD
SI
10
SI
9
SI
8
SI
7
SI
6
SI
5
SI
4
SI
3
V
DD
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
