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TMC22191 参数 Datasheet PDF下载

TMC22191图片预览
型号: TMC22191
PDF下载: 下载PDF文件 查看货源
内容描述: 数字视频编码器/分层引擎 [Digital Video Encoders/Layering Engine]
分类和应用: 编码器
文件页数/大小: 60 页 / 394 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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TMC22091/TMC22191  
PRODUCT SPECIFICATION  
Table 5. CLUT Locations Addressed by  
Overlay Inputs (TMC22191)  
Table 5. CLUT Locations Addressed by  
Overlay Inputs (TMC22191) (continued)  
OL4-0  
00  
CLUT location  
OL4-0  
1E  
CLUT location  
No Overlay  
FE  
FF  
01  
01  
02  
1F  
02  
Color-space Conversion in the Matrix  
When the input pixels are in RGB, GBR, or color-index for-  
mat and the CLUT is bypassed (TMC22191), the Matrix  
remains enabled, converting RGB data to color-difference  
format. When the input pixels are in 444 format  
(YC C 444, RGB, GBR, CI), the Interpolator (which con-  
verts 422 to 444) is not active. When the input pixels are in  
0E  
0F  
10  
11  
12  
0E  
0F  
No Overlay  
F1  
B R  
YC C format, the CLUT is enabled to scale the data to  
B R  
color-difference values and the Matrix is inactive. In color-  
index mode, the Matrix is active, converting the RGB CLUT  
output data to color-difference values.  
F2  
Table 6. Pixel Input Operation for Format Control Register bit 6 = HIGH (TMC22191)  
Format Control Register Pixel Data Format  
FORMAT  
INMODE  
BYPASS = LOW  
BYPASS = HIGH  
Bit 3,2  
Bit 1,0  
CLUT bypassed  
CLUT enabled  
00 (RGB)  
00 (444)  
01 (422)  
10 (15-bit)  
11 (CI)  
xx  
RGB  
YC C 444  
B R  
00  
00  
RGB  
YC C 422  
B R  
RGB  
RGB15  
CI  
00  
RGB  
01  
reserved  
GBR  
reserved  
10 (GBR)  
10  
00 (444)  
01 (422)  
10 (15-bit)  
11 (CI)  
xx  
YC C 444  
B R  
GBR  
YC C 422  
B R  
10  
GBR  
GBR15  
CI  
10  
GBR  
11  
not allowed  
not allowed  
Format Control Register Bit 6 = HIGH  
Format Control Register Bit 6 = LOW  
MSB  
LSB  
0
MSB  
LSB  
0
16 15  
8 7  
16 15  
8 7  
23  
23  
Pixel 1  
Pixel 2  
Pixel 3  
Pixel 4  
Pixel 1  
Pixel 2  
Pixel 3  
Pixel 4  
Y1  
Y2  
Y3  
Y4  
CB1  
CB1  
CB3  
CB3  
CR1  
CR1  
CR3  
CR3  
Y1  
Y2  
Y3  
Y4  
CB1  
CR1  
CB3  
CR3  
Pixel n  
Pixel n  
Yn  
Yn+1  
CBn  
CBn  
CRn  
CRn  
Yn  
Yn+1  
CBn  
CRn  
Pixel n+1  
Pixel n+1  
27003A  
Note: The pixel input sequence begins on the first LDV pulse after PDC goes HIGH. n = Odd number  
Figure 2. Pixel Data (PD ) Sequence for YC C 422  
23-0  
B R  
24  
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