PRODUCT SPECIFICATION
TMC22x5yA
*
Sync Pulse Generator
HBLK (Horizontal Blanking Period)
The horizontal blanking period is LOW between the start of
SAV and the end of EAV. This signal is used in several
places:
a) To clear the SYSPH offset when LOW, this is required
for correct operation of the subcarrier phase locked loop,
b) To aid in the comb filter management,
c) To remove the burst envelope on the demodulated UV
data,
The vertical and horizontal references to the decoder can be
from external VSYNC and HSYNC pulses, decoded from
TRS and TRS-ID words, or from the internal sync separator
which extracts the sync information from the digitized input
video.
The sync pulse generator (SPG) provides all the clock and
enable pulses required to synchronize the decoder operation
to the incoming video signal. These pulses are described
below, along with the microprocessor data required to
control them.
d) To remove the syncs on the BLUE and RED outputs.
BBLK (Vertical Burst Blanking Period)
The vertical burst blanking blanks the lines with no burst
from the burst phase locked loop. This signal is decoded from
Internal Field and Line Numbering Scheme
the line ident, LID , and is modified by the video standard
4-0
The internal line numbering of the digital decoder differs
from the standard video line numbering as shown in the
following tables. The internal line numbers for a 3 line comb
advance the numbering by 1 line with respect to the input,
but are identical with respect to the internally one line
delayed decoded video.
and the field count.
MBLK (Mixed Blanking)
This signal is used in the matrix to switch between the
sync scalar and the luma scalar. The MBLK signal is active
whenever HBLK is active or becomes active when VBLK
becomes active. MBLK is also active in PAL on line 310
when both VACT1 and FLD are HIGH and in NTSC and
PAL M on line 259 when VACT2 is HIGH and FLD is LOW.
Table 15. NTSC Field and Line Numbering
Standard Standard
Internal
Field #
Internal Line
#
*
Field #
1 & 3
1 & 3
2 & 4
2 & 4
Line #
FLD
The FLD is LOW for field 1 and HIGH for field 2.
1 - 3
1 & 3
0 & 2
0 & 2
1 & 3
260 - 262
0 - 259
*
4 - 263
LID
4-0
The line ID signals are used in the vertical comb filter
management to control the comb filter on the leading and
trailing lines of active video around the vertical blanking
period, to start and stop the VINDO operation, and in gener-
ating the vertical blanking and burst blanking periods.
264 - 265
266 - 525
260 - 261
0 - 259
Table 16. PAL B,G,H,I Field and Line Numbering
Standard Standard
Internal
Field #
Internal Line
#
*
VACT2
Field #
1 & 5
2 & 6
3 & 7
4 & 8
Line #
VACT2 is HIGH during the second half of all active lines.
1 - 312
0 & 4
1 & 5
2 & 6
3 & 7
0 - 311
0 - 312
0 - 311
0 - 312
*
GRABF
313 - 625
626 - 937
938 - 1250
The GRABF signal goes HIGH when the internal field count
is equal to the programmed field number for the GRAB
operation. f a pixel grab is being, this signal is held HIGH to
not inhibit the GRABS signal on each line.
*
Table 17. PAL M Field and Line Numbering
GRABL
The GRABL signal goes HIGH when the internal line count
is equal to the programmed line number for the GRAB
operation. If a pixel grab is being performed, this signal is
held HIGH to not inhibit the GRABS signal on each line.
Standard Standard
Internal
Field #
Internal Line
#
Field #
1 & 5
2 & 6
3 & 7
4 & 8
Line #
1 - 262
0 & 2
1 & 3
0 & 2
1 & 3
0 - 261
0 - 262
0 - 261
0 - 262
263 - 525
1 - 262
*
GRABP
The GRABP signal goes HIGH when the internal pixel count
is equal to the programmed pixel number for the GRAB
operation.
263 - 525
*
HSTBG (Burst gate)
DVSYNC and DHSYNC (Output Pins)
The burst gate starts the 16 clock period average of the
demodulated burst envelope. The position of the burst gate is
programmed into a register as the number of clock periods
from the falling edge of sync to the burst envelope.
The DVSYNC and DHSYNC signals are active when GCR2
is LOW. When GCR2 is HIGH these signals are three stated.
Three line comb based decoders have an inherent line delay,
therefore the input VSYNC and HSYNC signals can not be
just delayed by a few registers and output as DVSYNC and
DHSYNC: they need to be delayed by one complete line. In
all other comb filter configurations the DVSYNC and
* Signal is available over the microprocessor data bus.
REV. 1.0.0 2/4/03
59
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