PRODUCT SPECIFICATION
TMC22x5yA
assumed to be luminance and the high frequency portion is
processed as chrominance to find the magnitude and phase of
the chrominance vector. These three components are then
compared across the (0H & 1H) and (1H & 2H) taps of the
comb filter to produce the difference in luminance, chromi-
nance magnitude, and chrominance phase. These differences
are then translated in the user-programmable lookup table to
produce the “K” signal which controls the complementary
mix between the output of the comb filter and the simple
bandsplit decoder. That is, the “K” signals controls how
much of the combed high frequency luminance signal is sub-
tracted from the simple bandsplit chrominance for chroma
combs, or added to the low frequency output of the bandsplit
for luma comb filters.
Parallel and Serial Microprocessor Interfaces
The parallel microprocessor interface employs 12 pins, the
serial port uses 5. A single pin, SER, selects between the two
interface modes.
In parallel interface mode, one address line is decoded for
access to the internal control register and its pointer.
Controls are reached by loading a desired address through
the 8-bit D
7-0
port, followed by the desired data (read or
write) for that address. The control register address pointer
auto-increments to address 3Fh and then remains there.
A 2-line serial interface may also be used for initialization
and control. The same set of registers accessed by the paral-
lel port is available to the serial port. The device address in
the serial interface is selected via pins SA
2-0
.
The RESET pin sets all internal state machines to their ini-
tialized conditions and places the decoder in a power-down
mode. All register data are maintained while in power-down
mode.
Output Processor
The demodulated chrominance signal and the luminance
signal are passed through a programmable output matrix,
producing RGB, YUV, or YC
B
C
R
. When the clock is at
27MHz, a D1 signal can be produced on the R/V output with
the embedded TRS words fixed to the external HSYNC and
VSYNC timing.
Pin Assignments
100
1
81
80
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Name
G/Y
1
G/Y
0
LDV
GND
V
DD
B/Cb
9
B/Cb
8
B/Cb
7
B/Cb
6
B/Cb
5
B/Cb
4
B/Cb
3
B/Cb
2
B/Cb
1
B/Cb
0
GND
V
DD
R/Cr
9
R/Cr
8
R/Cr
7
R/Cr
6
R/Cr
5
R/Cr
4
R/Cr
3
R/Cr
2
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
R/Cr
1
R/Cr
0
GND
V
DD
DREF
FID
0
FID
1
FID
2
DHSYNC
DVSYNC
D
0
D
1
D
2
GND
V
DD
D
3
D
4
D
5
D
6
D
7
GND
V
DD
HSYNC
VSYNC
BUFFER
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
RESET
SET
SER
SA
0
SA
1
SA
2
GND
SDA
SCL
CS
R/W
A
0
A
1
GND
V
DD
VIDEOB
0
VIDEOB
1
VIDEOB
2
VIDEOB
3
VIDEOB
4
VIDEOB
5
VIDEOB
6
VIDEOB
7
VIDEOB
8
VIDEOB
9
Pin Name
76
GND
77
VIDEOA
0
VIDEOA
1
78
VIDEOA
2
79
VIDEOA
3
80
81
VIDEOA
4
82
VIDEOA
5
VIDEOA
6
83
84
VIDEOA
7
VIDEOA
8
85
86
VIDEOA
9
87
MASTER
0
MASTER
1
88
89
CLOCK
90
GND
91
V
DD
GND
92
G/Y
9
93
G/Y
8
94
95
G/Y
7
96
G/Y
6
G/Y
5
97
G/Y
4
98
99
G/Y
3
100 G/Y
2
30
31
50
65-22x5y-03
51
REV. 1.0.0 2/4/03
5
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
