PRODUCT SPECIFICATION
TMC22071A
GVSYNC and GRS data will continue. The GRS data will
be the initial subcarrier frequency and phase values selected
by the Format select bits of the Control Register. The
TMC22071A will acquire and lock to incoming video within
two frames after video is restored.
Subcarrier frequency, subcarrier phase, and Field ID data
(GRS) are transmitted in 4-bit nibbles over CVBS
3-0
during
the horizontal sync tip period at the PXCK rate.
Microprocessor Interface
Since microprocessor buses are notoriously noisy from a
wide-band analog point of view, the microprocessor inter-
face bus is only one bit wide, rather than the more customary
eight. The operation of this bus is similar to other bus-
controlled devices except that the TMC22071A internal
Control Register is accessed one bit at a time.
A sequence of 47 bits is written to or read from the LSB of a
standard microprocessor port. Writing to or reading from the
secondary address results in the transfer of data to or from
the internal shift register.
The RESET input, when LOW, sets all internal state
machines to their initialized conditions. Returning the
RESET pin HIGH starts the signal acquisition sequence
which lasts until locking with the gain-adjusted and clamped
video signal is achieved.
Subcarrier Phase-Locked Loop
A fully-digital phase-locked loop is used to extract the phase
and frequency of the incoming color burst. These frequency
and phase values are output over the CVBS bus during the
horizontal sync period. Fairchild’s video decoder and gen-
lockable encoder chips will accept these data directly.
Back Porch Digital Clamp
A digital back-porch clamp is employed to ensure a constant
blanking level. It digitally offsets the data from the A/D con-
verter to set the back porch level to precisely 3C
h
for NTSC
and 40
h
for PAL. When the digital clamp is enabled, the
CVBS video output data is determined from the A/D conver-
sion result minus the back porch level + 3C
h
(40
h
for PAL).
Digitized Video Output
The digitized 8-bit video output is provided over an 8-bit
wide CVBS data port, synchronous with PXCK and LDV.
Pin Assignments
1 68
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Name
V
DD
CVBS
0
CVBS
1
CVBS
2
CVBS
3
CVBS
4
V
DD
D
GND
CVBS
5
CVBS
6
CVBS
7
GHSYNC
GVSYNC
VALID
D
GND
D
GND
LDV
Pin
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Name
V
DD
PXCK
D
GND
D
GND
V
DD
V
DDA
A
GND
V
DDA
V
DDA
A
GND
R
B
V
IN3
V
DDA
V
IN2
A
GND
V
DDA
V
IN1
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Name
A
GND
R
T
A
GND
V
REF
A
GND
V
DDA
A
GND
C
BYP
PFD IN
A
GND
DDS OUT
PXCK SEL
V
DDA
COMP
A
GND
D
GND
CLK IN
Pin
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Name
V
DD
CLK OUT
EXT PXCK
D
GND
D
GND
D
GND
V
DD
V
DD
A
0
R/W
CS
V
DD
RESET
D
GND
D
0
INT
D
GND
65-22071-02
3
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
