PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Status - Read Only (41)
7
6
5
4
3
2
1
0
LINEST
BGST
VACT2
PALODD
VFLY
FGRAB
LGRAB
PGRAB
Reg
Bit
7
Name
Description
Pixel count reset. Pixel count reset
41
41
41
41
41
41
41
41
LINEST
BGST
6
Start of burst gate. Start of burst gate
Half line flag. Half line flag
5
VACT2
PALODD
VFLY
4
PAL Ident. PAL Ident (low on NTSC lines)
Vertical count reset. Vertical count reset
Field grab. Field grab
3
2
FGRAB
LGRAB
PGRAB
1
Line grab. Line grab
0
Pixel grab. Pixel grab
Status - Read Only (42)
7
6
5
4
3
2
1
0
FLD
VBLK
HBLK
LID
Reg
Bit
7
Name
FLD
Description
Field flag (F in D1 output). Field flag (F in D1 output)
42
42
42
42
6
VBLK
HBLK
LID
Vertical blanking (V in D1 output). Vertical blanking (V in D1 output)
Horizontal blanking (H in D1 output). Horizontal blanking (H in D1 output)
Line identification. Line identification
5
4-0
Status - Read Only (43)
7
6
5
4
3
2
1
0
YGO
YGU
UBO
UBU
VRO
VRU
Reserved
Reg
Bit
7
Name
YGO
Description
43
43
43
43
43
43
43
Y/G overflow. Y/G overflow
6
YGU
Y/G underflow. Y/G underflow
5
UBO
C /B overflow. C /B overflow
B B
4
UBU
C /B underflow. C /B underflow
B B
3
VRO
C /R overflow. C /R overflow
R R
2
VRU
C /R underflow. C /R underflow
R
R
1-0
Reserved
Reserved.
REV. 1.0.0 2/4/03
37
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
