PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Output Control (0B)
7
6
5
4
3
2
1
0
FMT422
CDEC
YUVT
Reserved
DRSEN
DRSCK
Reg
Bit
Name
Description
Enables C C output mux. When HIGH, multiplexes the C and C data
0B
7
FMT422
B
R
B
R
onto the same data bus. The chroma or multiplexed C C output appears on
B R
the B/C output. The R/C output is forced low.
B
R
0B
0B
6
5
CDEC
YUVT
C C decimation enable. When HIGH, the C C data are decimated to
B R
0:2:2 in the output processor.
B
R
Enables D1 output. When HIGH, enables 4:2:2 multiplexed YC C onto the
B R
R/C data output with TRS words inserted into the output data stream. The Y
R
data are still available on the G/Y output and multiplexed C C is available on
B R
the B/U output.
0B
0B
0B
4-2
1
Reserved
DRSEN
DRSCK
Reserved, set to zero.
DRS output enable. When HIGH, enables the DRS onto the G/Y output.
DRS data rate. Sets the DRS output data rate.
0
DRSCK
Function
0
Embeds data bytes (8 bits) at PCK
clock rate
1
Embeds data nibbles (4 bits) at
PXCK clock rate
REV. 1.0.0 2/4/03
19
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