TMC22x5yA
PRODUCT SPECIFICATION
Reg Bit Name
Function
Y offset, msb
Reg Bit Name
Function
2D
2
YOFF1
Status - Read Only
8
2D 1-0 SG1
Msync gain, 2 msbs
7 lsbs of phase
V axis flip
40 7-0 DDSPH
DDS phase, 8 msbs
Pixel count reset
Start of burst gate
Half line flag
7-0
2E 7-1 SYSPH1
41
41
41
41
41
41
41
41
42
42
7
6
5
4
3
2
1
0
7
6
LINEST
BGST
6-0
2E
0
VAXIS1
2F 7-0 SYSPH1
8 msbs of phase
VACT2
PALODD
VFLY
14-7
Video Measurement
PAL Ident
30
30
30
30
30
30
30
30
7
6
5
4
3
2
1
0
set to zero
Vertical count reset
Field grab
LGF
Line grab flag
FGRAB
LGRAB
PGRAB
FLD
LGEN
Line grab enable
Ext line grab enable
reserved, set to zero
Pixel grab gate
Line grab
LGEXT
Pixel grab
Field flag (F in D1 output)
PGG
VBLK
Vertical blanking (V in D1
output)
PGEN
PGEXT
Pixel grab enable
Ext pixel grab enable
Pixel grab, 8 lsbs
Line grab, 8 lsbs
reserved, set to zero
Field grab number
Msb of line grab
Pixel grab, 3 msbs
G/Y grab, 8 msbs
B/U grab, 8 msbs
R/V grab, 8 msbs
reserved
42
5
HBLK
Horizontal blanking (H in
D1 output)
31 7-0 PG
7-0
7-0
42 4-0 LID
Line identification
Y/G overflow
32 7-0 LG
33
33 6-4 FG
43
43
43
43
43
43
7
6
5
4
3
2
YGO
YGU
UBO
UBU
VRO
VRU
7
Y/G underflow
C /B overflow
B
33
3
LG
8
C /B underflow
B
33 2-0 PG
34 7-0 GY
35 7-0 BU
36 7-0 RV
37 7-6
10-8
9-2
C /R overflow
R
C /R underflow
R
9-2
43 1-0
44
reserved
9-2
7
MONO
Color kill active
Frequency/Phase error
DRS signal
44 6-0 FPERR
45 7-0 DRS
37 5-4 GY
37 3-2 BU
37 1-0 RV
G/Y grab, 2 lsbs
B/U grab, 2 lsbs
R/V grab, 2 lsbs
Luma grab, 8 msbs
Msync grab, 8 msbs
U grab, 8 msbs
1-0
1-0
1-0
46 7-0 PARTID
47 7-0 REVID
Reads back xx
h
Revision number
reserved
38 7-0
39 7-0
3A 7-0
3B 7-0
3C 7-6
3C 5-4
3C 3-2
3C 1-0
Y
9-2
48- 7-0
4A
M
9-2
U
9-2
9-2
1-0
4B
7
PKILL
Phase kill from comb fail
Comb filter status
XLUT output
V
Y
V grab, 8 msbs
4B 6-5 CFSTAT
4B 4-0 XOP
Luma grab, 2 lsbs
Msync grab, 2 lsbs
U grab, 2 lsbs
M
1-0
1-0
1-0
4C- 7-0
FF
reserved
U
Notes:
V
V grab, 2 lsbs
1. Functions are listed in the order of reading and writing.
Test Control
2. For each register listed above up to register 3F, all bits not
specified are reserved and must be set to zero to ensure
proper operation.
3D 7-0 TEST
3E 7-0 TEST
Must be set to zero
Must be set to zero
Vertical Blanking Control
3F
3F
7
6
VBIT20
V bit control
PEDDIS
Pedestal control
Closed caption control
3F 5-0 CCDEN
5-0
Auto-increment stops at 3F
10
REV. 1.0.0 2/4/03
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
