TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Comb Processor Control (07)
7
6
5
4
3
2
1
0
LS1BY
LS1IN
LS2DLY
SPLIT
BSFBY
BSFSEL
BSFMSB
GRSDLY
Reg
Bit
7
Name
LS1BY
LS1IN
Description
07
07
Line store 1 bypass. Bypasses linestore 1 when HIGH.
Line store 1 input. Selects the input of linestore 1:
6
LS1IN
Function
0
1
Primary Input
Secondary Input
07
07
5
4
LS2DLY
SPLIT
Line store 2 delay. LSTORE2 uses STS to store 1H when LOW and uses
VL to store SAV to EAV (or max count) when HIGH.
Line store 2 delay. Splits data through LSTORE2, 9 bits chroma and 7 bits
luma when HIGH (chroma combs) and 8 bits chroma and 8 bits luma when
LOW (luma comb).
07
07
3
2
BSFBY
Bandsplit filter bypass. Bandsplit filter is bypassed when HIGH.
Bandsplit filter select. Selects the bandsplit filter to be used:
BSFSEL
BSFSEL
Function
0
1
Select bandsplit filter response 1
Select bandsplit filter response 2
07
07
1
0
BSFMSB
GRSDLY
Inverts msb of bandsplit filter. When HIGH, inverts the msb of the input to
the bandsplit filter.
Delays input to GRS decode. When HIGH, delays the input to the GRS
extraction circuit by 1H. Genlock only.
Mid-Sync Level (08)
7
6
5
4
3
2
1
0
MIDS
Reg
Bit
Name
Description
08
7-0
MIDS
Mid sync level. Sets the mid point of syncs for the mixed sync separator, in
the subcarrier locked mode.
16
REV. 1.0.0 2/4/03
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
