PRODUCT SPECIFICATION
TMC2011A/2111A
Pin Descriptions – TMC2011A
Pin Number
Pin Name
Power
V
DD
GND
Data Inputs
DI
7-0
12,11,10,
9,4,3,2,1
14,13,12,
10,5,4,3,2
Data Input.
Eight inputs are provided for the data, which pass through the
shift register unchanged. The eight inputs on the TMC2011A are divided
into two groups of four bits to allow mixed delay operation. The lengths of
these two groups are different when the Mode Control (MC) is HIGH (see
Table 1). When MC is LOW both groups have equal delays.
Data Output.
The outputs of the shift register are delayed relative to the
input signals. The amount of the delay is programmable (see Table 1).
The outputs remain valid for a minimum of t
HO
nanoseconds after the
leading edge of CLK. This allow the data to be latched into circuits with
non-zero hold time requirements.
Master Clock.
All inputs and outputs are synchronous and operate from a
single master clock. All operations occur on the rising edge of the master
clock.
Length Select.
The length select input is used to determine the register
delay of the TMC2011A. This input is registered and affects the output t
DO
after the clock edge after it is input to the device (see Timing Diagram).
Delay lengths are specified in Table 1.
Mode Control.
The Mode Control is used to select the special 4-bit wide
split mode. When HIGH, the delay on DO
7-4
is fixed at 18 stages, while
DO
3-0
have the delay specified by the length select. When MC is LOW, all
eight bits have equal delays as specified by the length select.
7
18
8
21,22
Supply Voltage.
The TMC2011A and operates from a single +5V supply.
All power and ground lines must be connected.
Ground.
The TMC2011A operates from a single +5V supply. All power
and ground lines must be connected.
DIP
PLCC
Pin Function Description
Data Outputs
DO
7-0
13,14,15,
16,21,22,
23,24
15,16,17,
18,26,27,
28,1
Controls
CLK
8
9
L
3-0
19,20,6,5
23,24,7,6
MC
17
20
3
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