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TMC2193KJC 参数 Datasheet PDF下载

TMC2193KJC图片预览
型号: TMC2193KJC
PDF下载: 下载PDF文件 查看货源
内容描述: 10位编码器 [10 Bit Encoder]
分类和应用: 商用集成电路编码器
文件页数/大小: 72 页 / 543 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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PRODUCT SPECIFICATION  
TMC2193  
List of Figures  
List of Tables  
Figure 1. Input Formats . . . . . . . . . . . . . . . . . . . . . .7  
Figure 2. 24 bit Input Format . . . . . . . . . . . . . . . . . .7  
Figure 3. CCIR656 Input Format . . . . . . . . . . . . . . .8  
Figure 4. 10 bit Input Format . . . . . . . . . . . . . . . . . .8  
Figure 5. 20 bit 4:2:2 Input Format . . . . . . . . . . . . .8  
Figure 6. 20 bit 4:4:4 Input Format . . . . . . . . . . . . .8  
Figure 7. Gamma Curves . . . . . . . . . . . . . . . . . . . .9  
Figure 8. Propagation Delay through the  
Table 1.  
Table 2.  
CSM Coefficient Range . . . . . . . . . . . . 10  
Expected Output Values for the  
CSM with YCBCR Inputs . . . . . . . . . . . 11  
Expected Output Values for the  
CSM with RGB Inputs. . . . . . . . . . . . . . 11  
Coefficient sets YCBCR inputs. . . . . . . 11  
Coefficient sets YCBCR inputs. . . . . . . 11  
PDC Edge Control . . . . . . . . . . . . . . . . 13  
Horizontal Line Equations. . . . . . . . . . . 14  
Horizontal Timing Specifications. . . . . . 15  
Vertical Interval Timing  
Table 3.  
Table 4.  
Table 5.  
Table 6.  
Table 7.  
Table 8.  
Table 9.  
Encoder . . . . . . . . . . . . . . . . . . . . . . . . .12  
Figure 9. Horizontal Timing . . . . . . . . . . . . . . . . . .15  
Figure 10. Horizontal Timing – Vertical Blanking . . .15  
Figure 11. Horizontal Timing – 1st Half-line. . . . . . .16  
Figure 12. Horizontal Timing – 2nd Half-line . . . . . .16  
Figure 13. NTSC Vertical Interval . . . . . . . . . . . . . .17  
Figure 14. PAL Vertical Interval . . . . . . . . . . . . . . . .19  
Figure 15. PAL-M Vertical Interval . . . . . . . . . . . . . .21  
Figure 16. Burst Envelope . . . . . . . . . . . . . . . . . . . .25  
Figure 17. Gaussian Filter Response . . . . . . . . . . .25  
Figure 18. Interpolation Filter. . . . . . . . . . . . . . . . . .27  
Figure 19. Interpolation Filter – Passband  
Specifications . . . . . . . . . . . . . . . . . . . . 16  
Table 10. Default Horizontal Timing  
Parameters . . . . . . . . . . . . . . . . . . . . . . 17  
Table 11. NTSC Field/Line Sequence and  
Identification . . . . . . . . . . . . . . . . . . . . . 18  
Table 12. PAL Field/Line Sequence and  
Identification . . . . . . . . . . . . . . . . . . . . . 20  
Table 13. PAL-M Field/Line Sequence and  
Identification . . . . . . . . . . . . . . . . . . . . . 22  
Detail . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
Table 14. Standard Subcarrier Parameters . . . . . 24  
Table 15. Line by Line Pedestal Enable . . . . . . . . 25  
Table 16. Closed Caption Line Selection . . . . . . . 26  
Table 17. D/A Outputs . . . . . . . . . . . . . . . . . . . . . 27  
Table 18. Ancillary Data Format. . . . . . . . . . . . . . 28  
Table 19. Ancillary Data Control – Phase . . . . . . 29  
Table 20. Ancillary Data Control Frequency. . . . . 29  
Table 21. Field Identification and Subcarrier  
Figure 20. X/SIN(X) Filter . . . . . . . . . . . . . . . . . . . .27  
Figure 21. Layering Engine . . . . . . . . . . . . . . . . . . .30  
Figure 22. Overlay Outputs . . . . . . . . . . . . . . . . . . .31  
Figure 23. Data Keying . . . . . . . . . . . . . . . . . . . . . .31  
Figure 24. Microprocessor Parallel Port –  
Write Timing . . . . . . . . . . . . . . . . . . . . . .32  
Figure 25. Microprocessor Parallel Port –  
Read Timing . . . . . . . . . . . . . . . . . . . . . .32  
Reset Modes . . . . . . . . . . . . . . . . . . . . 29  
Figure 26. Serial Port Read/Write Timing . . . . . . . .33  
Figure 27. Serial Interface – Typical Byte  
Table 22. Layering and Keying Modes . . . . . . . . . 30  
Table 23. Overlay Address Map. . . . . . . . . . . . . . 31  
Table 24. Parallel Port Control . . . . . . . . . . . . . . . 32  
Table 25. Serial Port Addresses. . . . . . . . . . . . . . 33  
Table 26. Control Register Map . . . . . . . . . . . . . . 35  
Transfer. . . . . . . . . . . . . . . . . . . . . . . . . .34  
Figure 28. Serial Interface – Chip Address . . . . . . .34  
Figure 29. Typical Analog Reconstruction Filter . . .65  
Figure 30. Overall Response . . . . . . . . . . . . . . . . . .65  
Figure 31. Typical Layout. . . . . . . . . . . . . . . . . . . . .67  
Figure 32. ST-163E Layout . . . . . . . . . . . . . . . . . . .68  
Figure 33. Pass Band . . . . . . . . . . . . . . . . . . . . . . .69  
Figure 34. Stop Band. . . . . . . . . . . . . . . . . . . . . . . .69  
Figure 35. 2T Pulse . . . . . . . . . . . . . . . . . . . . . . . . .69  
Figure 36. Group Delay . . . . . . . . . . . . . . . . . . . . . .69  
REV. 1.0 3/26/03  
3