TMC2011A/2111A
PRODUCT SPECIFICATION
Pin Descriptions – TMC2111A
Pin Number
Pin Name
Power
V
DD
GND
Data Inputs
DI
7-0
12,11,10,
9,4,3,2,1
14,13,12,
10,5,4,3,2
Data Input.
Eight inputs are provided for the data, which pass through the
shift register unchanged. The TMC2111A consists of a single group of
eight bits with all data bits having equal delays.
Data Output.
The outputs of the shift register are delayed relative to the
input signals. The amount of the delay is programmable (see Table 1).
The outputs remain valid for a minimum of t
HO
nanoseconds after the
leading edge of CLK. This allow the data to be latched into circuits with
non-zero hold time requirements.
Master Clock.
All inputs and outputs are synchronous and operate from a
single master clock. All operations occur on the rising edge of the master
clock.
Length Select.
The length select input is used to determine the register
delay of the TMC2111A. This input is registered and affects the output t
DO
after the clock edge after it is input to the device (see Timing Diagram).
Delay lengths are specified in Table 1.
7
17,18
8
20,21,22
Supply Voltage.
The TMC2111A operates from a single +5V supply. All
power and ground lines must be connected.
Ground.
The TMC2111A operates from a single +5V supply. All power
and ground lines must be connected.
DIP
PLCC
Pin Function Description
Data Outputs
DO
7-0
13,14,15,
16,21,22,
23,24
15,16,17,
18,26,27,
28,1
Controls
CLK
8
9
L
3-0
19,20,6,5
23,24,7,6
Table 1. Programming Length Controls
TMC2011A
Input Code
L
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4
L
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
L
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
L
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Mode (MC) =0
DO
3-0
Length
DO
7-4
Length
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Mode (MC) =1
DO
3-0
Length
DO
7-4
Length
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
TMC2111A
DO
7-0
Length
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
