TYPICAL INTERFACE CIRCUIT
The typical interface circuit using the comparator is shown
in figure 2. Although it needs few external components
and is easy to apply, there are several conditions that
should be noted to achieve optimal performance. The very
high operating speeds of the comparator require careful
layout, decoupling of supplies, and proper design of trans-
mission lines.
Since the SPT9693 comparator is a very high-frequency
and high-gain device, certain layout rules must be followed
to avoid oscillations. The comparator should be soldered
to the board with component lead lengths kept as short as
possible. A ground plane should be used, while the input
impedance to the part is kept as low as possible, to de-
crease parasitic feedback. If the output board traces are
longer than approximately half an inch, microstripline
techniques must be employed to prevent ringing on the
output waveform. Also, the microstriplines must be termi-
nated at the far end with the characteristic impedance of
the line to prevent reflections. All supply voltages should
be decoupled with high-frequency capacitors as close to
the device as possible. If using the SPT9693 as a single
comparator, the outputs of the inactive comparator can be
grounded, left open or terminated with 50 ohms to –2 V. All
outputs on the active comparator, whether used or un-
used, should have identical terminations to minimize
ground current switching transients.
All ground pins should be connected to the same ground
plane to further improve noise immunity and shielding.
Unused outputs must be terminated with 50 ohms to
ground.
Figure 2 – SPT9693 Typical Interface Circuit
AV
CC
AV
EE
GND
Figure 3 – SPT9693 Typical Interface Circuit
with Hysteresis
AV
CC
D2
D2
GND
AV
EE
.1 µF
.1 µF
.1 µF
V
IN
D2
+
Q Output
V
IN
D2
+
.1 µF
D2
D2
Q Output
V
Ref
LE
D2
LE
R
L
50
W
R
L
50
W
Q Output
V
Ref
LE
D2
LE
R
L
50
W
R
L
50
W
Q Output
D1
D1
550
W
V
C
»
5 V
2 V
.1 µF
550
W
V
C
»
5 V
1.3 V
0.1 µF
0.1 µF
2 V
Notes:
1) D1 = 1N5231B or 1N751 or equivalent.
2) D2 = 1N914 or equivalent.
3) At no time should
both
inputs be allowed to float with power applied
to the device. At least one of the inputs should be tied to a voltage
within the common mode range (3.0 to +8.0 V) to prevent possible
damage to the device. Additional protection diodes D2 should be used
on the inputs if there is the possibility of exceeding the absolute
maximum ratings.
100
W
0 to 200
W
2 V
Notes:
1) D1 = 1N5231B or 1N751 or equivalent.
2) D2 = 1N914 or equivalent.
3) At no time should
both
inputs be allowed to float with power applied
to the device. At least one of the inputs should be tied to a voltage
within the common mode range (3.0 to +8.0 V) to prevent possible
damage to the device. Additional protection diodes D2 should be
used on the inputs if there is the possibility of exceeding the absolute
maximum ratings.
SPT9693
7
3/1/01
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
