SWITCHING TERMS (Refer to figure 1)
t
pdH
INPUT TO OUTPUT HIGH DELAY – the propaga-
tion delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output LOW to HIGH transition
t
pdL
INPUT TO OUTPUT LOW DELAY – the propagation
delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output HIGH to LOW transition
t
pLOH
LATCH ENABLE TO OUTPUT HIGH DELAY – the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output LOW to HIGH transition
V
OD
VOLTAGE OVERDRIVE – the difference between
the differential input and reference input voltages
t
pLOL
LATCH ENABLE TO OUTPUT LOW DELAY – the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output HIGH to LOW transition
t
H
MINIMUM HOLD TIME – the minimum time after the
negative transition of the Latch Enable signal that
the input signal must remain unchanged in order to
be acquired and held at the outputs
MINIMUM LATCH ENABLE PULSE WIDTH – the
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change
MINIMUM SET-UP TIME – the minimum time before
the negative transition of the Latch Enable signal
that an input signal change must be present in order
to be acquired and held at the outputs
t
pL
t
S
GENERAL INFORMATION
The SPT9689 is an ultrahigh-speed dual voltage com-
parator. It offers tight absolute characteristics. The device
has differential analog inputs and complementary logic
outputs compatible with ECL systems. The output stage is
adequate for driving terminated 50 ohm transmission
lines.
The SPT9689 has a complementary latch enable control
for each comparator. Both should be driven by standard
ECL logic levels.
The negative common mode voltage is –2.5 V. The posi-
tive common mode voltage is +4.0 V.
The dual comparators share the same V
CC
and V
EE
con-
nections but have separate grounds for each comparator
to achieve high crosstalk rejection.
Figure 2 – Internal Function Diagram
Q
V
IN
V
IN
+
PRE
AMP
LATCH
ECL
OUT
Q
REF
1
REF
2
CLK
BUF
V
EE
V
CC
GND
LE
LE
SPT9689
4
2/20/01
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
