SWITCHING TERMS (Refer to figure 1)
t
pdH
INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal
crosses the reference voltage (± the input offset
voltage) to the 50% point of an output LOW to HIGH
transition.
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output HIGH to LOW transition.
GENERAL INFORMATION
The SPT9687 is an ultrahigh-speed dual voltage compara-
tor. It offers tight absolute characteristics. The device has
differential analog inputs and complementary logic outputs
compatible with ECL systems. The output stage is adequate
for driving terminated 50 ohm transmission lines.
The SPT9687 has a complementary latch enable control for
each comparator. Both should be driven by standard ECL logic
levels.
The dual comparator shares the same V
CC
and V
EE
connec-
tions but have separate grounds for each comparator to
achieve high crosstalk rejection.
Figure 2 - Internal Functional Diagram
t
pdL
t
pLOH
LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
50% point of an output LOW to HIGH transition.
V
OD
VOLTAGE OVERDRIVE - The difference between
the differential input and the reference voltages.
Q
V
IN
+
-
t
pLOL
LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to the
50% point of an output HIGH to LOW transition.
t
H
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
PRE
AMP
LATCH
ECL
OUT
V
IN
Q
REF
1
REF
2
CLK
BUF
V
EE
V
CC
GND1
LE
LE
GND2
TYPICAL INTERFACE CIRCUIT
The typical interface circuit using the comparator is shown
in figure 3. Although it needs few external components
and is easy to apply, there are several conditions that
should be met to achieve optimal performance. The very
high operating speeds of the comparator require careful
layout, decoupling of supplies, and proper design of trans-
mission lines.
Since the SPT9687 comparator is a very high frequency and
high gain device, certain layout rules must be followed to
avoid spurious oscillations. The comparator should be sol-
dered to the board with component lead lengths kept as short
as possible. A ground plane should be used, and the input
impedance to the part should be kept as low as possible to
decrease parasitic feedback. If the output board traces are
longer than approximately one-half inch, microstripline tech-
niques must be employed to prevent ringing on the output
waveform. Also, the microstriplines must be terminated at
the far end with the characteristic impedance of the line to
prevent reflections. All supply voltage pins should be de-
coupled with high frequency capacitors as close to the
device as possible. All ground and N/C pins should be
connected to the same ground plane to further improve noise
immunity and shielding. If using the SPT9687 as a single
comparator, the outputs of the inactive comparator can be
grounded, left open or terminated with 50 Ohms to -2 V. All
outputs on the active comparator, whether used or unused,
should have identical terminations to minimize ground cur-
rent switching transients.
Note: To ensure proper power up of the device, the input
should be kept below +1.5 V during power up.
SPT9687
4
3/21/97
t
pL
t
S
TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
The latch enable (LE) pulse is shown at the top. If LE is high
and LE low in the SPT9687, the comparator tracks the
input difference voltage. When LE is driven low and LE
high, the comparator outputs are latched into their existing
logic states.
The leading edge of the input signal (which consists of a
50 mV overdrive voltage) changes the comparator output
after a time of t
pdL
or t
pdH
(Q or Q ). The input signal must be
maintained for a time t
s
(set-up time) before the LE falling
edge and LE rising edge and held for time t
H
after the falling
edge for the comparator to accept data. After t
H
, the output
ignores the input status until the latch is strobed again. A
minimum latch pulse width of t
pL
is needed for strobe
operation, and the output transitions occur after a time of
t
pLOH
or t
pLOL
.
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
