欢迎访问ic37.com |
会员登录 免费注册
发布采购

SPT9101SIS 参数 Datasheet PDF下载

SPT9101SIS图片预览
型号: SPT9101SIS
PDF下载: 下载PDF文件 查看货源
内容描述: 125 MSPS采样保持放大器 [125 MSPS SAMPLE-AND-HOLD AMPLIFIER]
分类和应用: 放大器光电二极管
文件页数/大小: 8 页 / 180 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
 浏览型号SPT9101SIS的Datasheet PDF文件第1页浏览型号SPT9101SIS的Datasheet PDF文件第2页浏览型号SPT9101SIS的Datasheet PDF文件第3页浏览型号SPT9101SIS的Datasheet PDF文件第5页浏览型号SPT9101SIS的Datasheet PDF文件第6页浏览型号SPT9101SIS的Datasheet PDF文件第7页浏览型号SPT9101SIS的Datasheet PDF文件第8页  
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions: All parameters having min/
max specifications are guaranteed. The Test
Level column indicates the specific device test-
ing actually performed during production and
Quality Assurance inspection. Any blank sec-
tion in the data column indicates that the speci-
fication is not tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
=25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= 25
°C.
Parameter is
guaranteed over specified temperature range.
Figure 1 - Timing Diagram
Input
Acquisition
Time
Observed at
Hold Capacitor
Aperature
Delay
Output
Observed at
Amplifier Output
Track-to-Hold
Settling
CLK
Hold
Track
Hold
NCLK
TIMING SPECIFICATION DEFINITIONS
ACQUISITION TIME
This is the time it takes the SPT9101 to acquire the analog
signal at the internal hold capacitor when it makes a transition
from hold mode to track mode. (See figure 1.) The acquisition
time is measured from the 50% input clock transition point to
the point when the signal is within a specified error band at the
internal hold capacitor (ahead of the output amplifier). It does
not include the delay and settling time of the output amplifier.
Because the signal is internally acquired and settled at the
hold capacitor before the output voltage has settled, the
sampler can be put in hold mode before the output has settled.
TRACK-TO-HOLD SETTLING TIME
The time required for the output to settle to within 4 mV of its
final value.
APERTURE DELAY
The aperture delay time is the interval between the leading
edge transition of the clock input and the instant when the
input signal was equal to the held value. It is the difference
in time between the digital hold switch delay and the analog
signal propagation time. Because the analog propagation
time is longer than the digital delay in the SPT9101, the
aperture delay is a negative value.
SPT9101
4
12/30/99