ELECTRICAL SPECIFICATIONS
+V
S
=+5.0 V, -V
S
=-5.2 V, R
LOAD
=100
Ω,
unless otherwise specified.
PARAMETERS
Hold Mode Dynamics
Worst Harmonic
V
Out
= 2 V p-p
Worst Harmonic
V
Out
= 2 V p-p
Worst Harmonic
V
Out
= 2 V p-p
Worst Harmonic
V
Out
= 2 V p-p
Sampling Bandwidth
2
V
IN
= 0.5 V p-p
Hold Noise
3
(RMS)
Droop Rate
Feedthrough Rejection (50 MHz)
V
Out
= 2 V p-p
Maximum Hold Time, V
IN
=0 V
Track-and-Hold Switching
Aperture Delay
Aperture Jitter
Pedestal Offset, V
IN
=0 V
Transient Amplitude
Settling Time to 4 mV
Glitch Product
4
V
IN
= 0 V
Hold-to-Track Switching
Acquisition Time to 0.1%
2 V Output Step
Acquisition Time to 0.01%
2 V Output Step
Power Supply
5
+V
S
Voltage
-V
S
Voltage
Power Dissipation
TEST
CONDITIONS
23 MHz, 50 MSPS
+25
°C
48 MHz, 100 MSPS
+25
°C
48 MHz, 100 MSPS
Full Temp.
48 MHz, 125 MSPS
+25
°C
-3 dB, +25 ˚C
+25
°C
V
IN
=0.0 V, +25
°C
Full Temp.
Full Temp.
+25
°C
+25
°C
+25
°C
Full Temp.
V
IN
= 0 V, Full Temp.
Full Temp.
+25
°C
TEST
LEVEL
V
IV
IV
V
V
V
V
V
IV
V
V
I
VI
V
V
V
SPT9101
MIN
TYP
-75
-62
MAX
UNITS
dB FS
-57
-53
dB FS
dB FS
dB FS
MHz
mV/s
mV/µs
dB
ns
ps
ps rms
mV
mV
mV
ns
pV-s
-57
350
150 x t
H
-40
-66
100
200
-250
<1
±10
8
4
20
±25
±35
+25
°C
+25
°C
Full Temp.
Full Temp, Track Mode
Full Temp, Clocked Mode
Full Temp, Track Mode
Full Temp, Clocked Mode
Full Temp, Track Mode
Full Temp, Clocked Mode
V
IV
IV
VI
VI
VI
VI
VI
VI
7
11
14
16
65
55
65
55
663
561
ns
ns
ns
mA
mA
mA
mA
mW
mW
54
44
54
44
551
449
1
Time to recover within rated error band from 160% overdrive.
2
Sampling bandwidth is defined as the -3 dB frequency response of the input sampler to the hold capacitor when operating in the
sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier.
3
Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (t
H
) is 20 ns, the accumulated
noise is typically 3
µV
(150 mV/s x 20 ns). This value must be combined with the track mode noise to obtain total noise.
Typical thermal impedances:
4
Total energy of worst case track-to-hold or hold-to-track glitch.
ΘJC
(LCC) = +6
°C/W
ΘJA
(SOIC) = +85
°C/W
in still air at +25
°C
ambient.
5
Clocked mode is specified with a 50% clock duty cycle.
6
Analog input voltage should be limited
≤0.8
volts to maintain device in linear range.
SPT9101
3
12/30/99
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
