Figure 2 – Typical Interface Circuit
CLK IN
Out of Range Bit
OGND
DGND
CLK
+
D12
D11
D10
D9
MSB
U1
DGND
V
IN
R
SPT7937
+A5
+
AV
DD
D8
D7
D6
D5
D4
D3
D2
D1
D0
OV
DD
1
LSB
(DUT)
A
IN
+A5
U1
+
V
IN
RGND
V
RHS
V
RHF
V
RLF
V
RLS
28
TK11240B
Ext V
REF
(+4 V)
DV
DD2
FB
+
+D3/5V
+A5
+
10 F
+A5
AGND
+D3/5V
+D3/5
+
10 F
+D3/5
DGND
Notes:
1) Unless otherwise specified, all non-polarized capacitors are 0.01 microfarad
surface-mount chip capacitors. They need to be placed as close to the pin as possible
2) All polarized capacitors are 4.7 to 10 microfarad tantalum surface-mount capacitors
3) FB is a ferrite bead. Place FB as close to the DUT as possible
4) U1 is TOKO regulator TK11240B (4.0 V)
TYPICAL INTERFACE CIRCUIT
Very few external components are required to achieve the
stated device performance. Figure 2 shows the typical in-
terface requirements when using the SPT7937 in normal
circuit operation. The following sections provide descrip-
tions of the major functions and outline critical perfor-
mance criteria to consider for achieving the optimal device
performance.
POWER SUPPLIES AND GROUNDING
CADEKA suggests that both the digital (DV ) and the ana-
DD
log (AV
DD
) supply voltages on the SPT7937 be derived
from a single analog supply as shown in figure 2. A sepa-
rate digital supply should be used for the digital output
driver supply (OV
DD
) and all interface circuitry. CADEKA
suggests using this power supply configuration to prevent
a possible latch-up condition on power up. In addition, the
power supplies must be powered up before the analog in-
put is applied.
Interfacing Logic
DV
DD
SPT7937
6
3/5/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
