CLOCK
The SPT7935 accepts a low voltage CMOS logic level at
the CLK input. The duty cycle of the clock should be kept as
close to 50% as possible. Because consecutive stages in the
ADC are clocked in opposite phase to each other, a non-50%
duty cycle reduces the settling time available for every other
stage and thus potentially causing a degradation of dynamic
performance.
For optimal performance at high input frequencies, the clock
should have low jitter and fast edges. The rise/fall times
should be kept shorter than 2 ns. Overshoot and undershoot
should be avoided. Clock jitter causes the noise floor to rise
proportional to the input frequency. Because jitter can be
caused by crosstalk on the PC board, it is recommended that
the clock trace be kept as short as possible and standard
transmission line practices be followed.
DIGITAL OUTPUTS
The digital output data appears in an offset binary code at
3.3 V CMOS logic levels. A negative full scale input results in
an all zeros output code (000…0). A positive full scale input
results in an all 1’s code (111…1). The output data is available
7.5 clock cycles after the data is sampled. The input signal is
sampled on the high to low transition of the input clock. Output
data should be latched on the low to high clock transition as
shown in figure 1, the Timing Diagram. The output data is
invalid for the first 20 clock cycles after the device is powered up.
EVALUATION BOARD
The EB7935 Evaluation Board is available to aid designers in
demonstrating the full performance capability of the
SPT7935. The board includes an on-board clock driver,
adjustable voltage references, adjustable bias current cir-
cuits, single-to-differential input buffers with adjustable lev-
els, a single-to-differential transformer (1:1), digital output
buffers and 3.3/5 V adjustable logic outputs. An application
note (AN7935) is also available which describes the opera-
tion of the evaluation board and provides an example of the
recommended power and ground layout and signal routing.
Contact the factory for price and availability.
PACKAGE OUTLINE
44L TQFP
A
B
INCHES
SYMBOL
A
B
C
D
E
F
C
D
MILLIMETERS
MAX
MIN
12.00 Typ
10.00 Typ
10.00 Typ
12.00 Typ
0.80 Typ
0.018
0.057
0.006
0.030
0.300
1.35
0.05
0.450
1.00 Typ
0-7°
0.45
1.45
0.15
0.750
MAX
MIN
0.472 Typ
0.394 Typ
0.394 Typ
0.472 Typ
0.031 Typ
0.012
0.053
0.002
0.018
0.039 Typ
0-7°
G
H
I
J
K
Index
Pin 1
E
F
G
I
H
J
K
SPT7935
7
7/12/00
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
