Figure 4 – Ladder Force/Sense Circuit
Figure 5 – Simplified Reference Ladder Drive Circuit
Without Force/Sense Circuit
+4.0 V
External
Reference
VRHS
(+3.85 V)
+
-
1
VRHF
150 mV
R/2
2
VRHS
R
R
3
VRLS
R
R=30
Ω
(typ)
All capacitors are 0.01 µF
R
VOLTAGE REFERENCE
The SPT7852 requires the use of a single external voltage
reference for driving the high side of the reference ladder. It
must be within the range of 3 V to 5 V. Both ADCs share the
same reference ladder. The lower side of the ladder is typi-
cally tied to AGND (0.0 V), but can be run up to 2.0 V with a
second reference. The analog input voltage range will track
the total voltage difference measured between the ladder
sense lines, V
RHS
and V
RLS
.
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line volt-
ages across part-to-part and temperature variations. By us-
ing the configuration shown in figure 4, offset and gain er-
rors of less than
±2
LSB can be obtained.
In cases where wider variations in offset and gain can be
tolerated, V
Ref
can be tied directly to V
RHF
and AGND can
be tied directly to V
RLF
as shown in figure 5. Decouple force
and sense lines to AGND with a .01
µF
capacitor (chip cap
preferred) to minimize high-frequency noise injection. If this
simplified configuration is used, the following considerations
should be taken into account:
The reference ladder circuit shown in figure 5 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Typically, the top side voltage drop for
V
RHF
to V
RHS
will equal:
V
RHF
– V
RHS
= 3.75% of (V
RHF
– V
RLF
) (typical),
and the bottom side voltage drop for V
RLS
to V
RLF
will equal:
V
RLS
– V
RLF
= 3.75% of (V
RHF
– V
RLF
) (typical).
Figure 5 shows an example of expected voltage drops for a
specific case. V
Ref
of 4.0 V is applied to V
RHF
and V
RLF
is
+
-
4
VRLF
AGND
VRLS
(0.150 V)
VRLF (AGND)
0.0 V
150 mV
R
R
5
R/2
All capacitors are 0.01 µF
tied to AGND. A 150 mV drop is seen at V
RHS
(= 3.85 V) and
a 150 mV increase is seen at V
RLS
(= 0.150 V).
ANALOG INPUT
V
INA
and V
INB
are the analog inputs for channel A and chan-
nel B, respectively. Both channels share the same refer-
ence ladder. The input voltage range is from V
RLS
to V
RHS
(typically 4.0 V) and will scale proportionally with respect to
the voltage reference. (See voltage reference section.)
The drive requirements for the analog inputs are very mini-
mal when compared to most other converters due to the
SPT7852’s extremely low input capacitance of only 5 pF
and very high input resistance of 50 kΩ.
The analog input should be protected through a series resis-
tor and diode clamping circuit as shown in figure 6.
Figure 6 – Recommended Input Protection Circuit
+V
AV
DD
D1
Buffer
47
Ω
D2
ADC
-V
D1 = D2 = Hewlett Packard HP5712 or equivalent
SPT7852
8
1/12/00
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
