ladder taps (V
ST
, V
RM
and V
SB
). V
ST
is the sense for the top
of the reference ladder (+2.0 V), V
RM
is the midpoint of the
ladder (0.0 V typ) and V
SB
is the sense for the bottom of the
reference ladder (-2.0 V). The voltages seen at V
ST
and V
SB
are the true full scale input voltages of the device when V
FT
and V
FB
are driven to the recommended voltages (+2.5 V and
-2.5 V typical respectively). These points should be used to
monitor the actual full scale input voltage of the device and
should not be driven to the expected ideal values as is
commonly done with standard flash converters. When not
being used, a decoupling capacitor of .01
µF
(chip cap
preferred) connected to AGND from each tap is recom-
mended to minimize high frequency noise injection.
Figure 3 - Analog Equivalent Input Circuit
VCC
ANALOG INPUT
V
IN
is the analog input. The full scale input range will be 80%
of the reference voltage or
±2
volts with V
FB
=-2.5 V and
V
FT
=+2.5 V.
The drive requirements for the analog inputs are minimal
when compared to conventional Flash converters due to the
SPT7820’s extremely low input capacitance of only 5 pF and
very high input resistance of 300 kΩ. For example, for an
input signal of
±2
V p-p with an input frequency of 10 MHz,
the peak output current required for the driving circuit is only
628
µA.
CLOCK INPUT
The SPT7820 is driven from a single-ended TTL input (CLK).
The CLK pulse width (tpwH) must be kept between 20 ns and
300 ns to ensure proper operation of the internal track-and-
hold amplifier. (See timing diagram.) When operating the
SPT7820 at sampling rates above 3 MSPS, it is recom-
mended that the clock input duty cycle be kept at 50% but
performance will not be degraded if kept within the range of
40-60%. The analog input signal is latched on the rising edge
of the CLK.
The clock input must be driven from fast TTL logic (V
IH
≤4.5
V, T
RISE
<6 ns). In the event the clock is driven from a
high current source, use a 100
Ω
resistor in series to current
limit to approximately 45 mA.
DIGITAL OUTPUTS
The format of the output data (D0-D9) is straight binary. (See
table II.) The outputs are latched on the rising edge of CLK
with a propagation delay of 14 ns (typ). There is a one clock
cycle latency between CLK and the valid output data. (See
the timing diagram.)
Table II - Output Data Information
ANALOG INPUT
>+2.0 V + 1/2 LSB
+2.0 V -1 LSB
0.0 V
-2.0 V +1 LSB
<-2.0 V
OVERRANGE
D1O
1
O
O
O
O
OUTPUT CODE
D9-DO
11 1111
11 1111
1111
111Ø
VIN
Analog Prescaler
VFT
VEE
An example of a reference driver circuit recommended is
shown in figure 2. IC1 is REF-03, the +2.5 V reference with a
tolerance of 0.6% or +/- 0.015 V. The potentiometer R1 is
10 kΩ and supports a minimum adjustable range of up to
150 mV. IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1% with good
TC tracking to maintain a 0.3 LSB matching between V
FT
and
V
FB
. If 0.1% matching is not met, then potentiometer R4 can
be used to adjust the V
FB
voltage to the desired level. V
FT
and
V
FB
should be adjusted such that V
ST
and V
SB
are exactly
+2.0 V and -2.0 V respectively.
The analog input range will scale proportionally with respect
to the reference voltage if a different input range is required.
The maximum scaling factor for device operation is
±
20% of
the recommended reference voltages of V
FT
and V
FB
. How-
ever, because the device is laser trimmed to optimize perfor-
mance with
±
2.5 V references, the accuracy of the device will
degrade if operated beyond a
±
2% range.
The following errors are defined:
+FS error = top of ladder offset voltage =
∆(+FS
-V
ST
+1 LSB)
-FS error = bottom of ladder offset voltage =
∆(-FS
-V
SB
-1 LSB)
where the +FS (full scale) input voltage is defined as the output
transition between 1-10 and 1-11 and the -FS input voltage is
defined as the output transition between 0-00 and 0-01.
ØØ ØØØØ ØØØØ
OO OOOO OOOØ
OO OOOO OOOO
(Ø indicates the flickering bit between logic 0 and 1).
The rise times and fall times of the digital outputs are not
symmetrical. The propagation delay of the rise time is typi-
cally 14 ns and the fall time is typically 6 ns. (See figure 4.)
The nonsymmetrical rise and fall times create approximately
8 ns of invalid data.
SPT7820
7
3/11/97
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
