Figure 4 - Recommended Input Protection Circuit
+V
AV
DD
CLOCK INPUT
The SPT7734 is driven from a single-ended TTL-input clock.
Because the pipelined architecture operates on the rising edge of
the clock input, the device can operate over a wide range of input
clock duty cycles without degrading the dynamic performance.
DIGITAL OUTPUTS
D1
Buffer
47
Ω
D2
ADC
The digital outputs (D0-D8) are driven by a separate supply
(OV
DD
) ranging from +3 V to +5 V. This feature makes it
possible to drive the SPT7734's TTL/CMOS-compatible out-
puts with the user's logic system supply. The format of the
output data (D0-D7) is straight binary. (See table III.) The
outputs are latched on the rising edge of CLK. These outputs
can be switched into a tri-state mode by bringing
EN
high.
Table III - Output Data Information
-V
D1 = D2 = Hewlett Packard HP5712 or equivalent
ANALOG INPUT
+F.S. + 1/2 LSB
OVERRANGE
D8
1
O
O
O
O
OUTPUT CODE
D7-D0
1111
1111
1111
111Ø
Figure 5 - On-Chip Protection Circuit
+F.S. -1/2 LSB
+1/2 F.S.
+1/2 LSB
ØØØØ ØØØØ
OOOO OOOØ
OOOO OOOO
V
DD
120
Ω
0.0 V
Analog
(Ø indicates the flickering bit between logic 0 and 1).
DO NOT CONNECT PINS (DNC)
120
Ω
Pad
There are two pins designated as Do Not Connect (DNC).
These pins must be left floating for proper operation of the
device.
OVERRANGE OUTPUT
The OVERRANGE OUTPUT (D8) is an indication that the
analog input signal has exceeded the positive full scale input
voltage by 1 LSB. When this condition occurs, D8 will switch
to logic 1. All other data outputs (D0 to D7) will remain at
logic 1 as long as D8 remains at logic 1. This feature makes
it possible to include the SPT7734 into higher resolution
systems.
SPT7734
7
1/27/98
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
