PIN ASSIGNMENTS
V
OUT1
V
OUT2
RGND
23
V
OUT3
V
REFB2345
V
REFT2345
V
DD
V
OUT4
RGND
45
V
OUT5
V
OUT6
CLR
(Active Low) Analog Clear. Sets the output
voltages to RGND. (Each RGND is common to a
DAC pair.)
CLR
does not reset the digital latches.
When
CLR
is brought back high, the DAC outputs
revert back to their original outputs as determined
by the data in their DAC latches.
When this logic input is taken low, the contents of
the input latches are transferred to their respective
DAC latches. (Active Low) Data is latched on
rising edge.
Addresses DAC0 to DAC7 for loading the eight
input latches.
Digital Inputs (D0 = LSB)
Top Reference Voltage for DACs 0 and 1
Top Reference Voltage for DACs 6 and 7
Bottom Reference Voltage for DACs 0 and 1
Bottom Reference Voltage for DACs 6 and 7
Reference Ground for Output Amplifiers 0 and 1
Reference Ground for Output Amplifiers 2 and 3
Reference Ground for Output Amplifiers 4 and 5
Reference Ground for Output Amplifiers 6 and 7
Output Voltage Pins for DAC0 – DAC7
Digital +5 V Supply
Analog +11.5 V Supply (Nominal)
Analog –8 V Supply (Nominal)
Ground
44
RGND
01
V
OUT0
V
REFB01
V
REFT01
V
DD
V
SS
LDAC
A2
A1
A0
CS
LDAC
RGND
67
V
OUT7
V
REFB67
V
REFT67
V
SS
1
A0 – A2
D0 – D12
V
REFT01
V
REFT67
V
REFB01
Top View
CLR
D12 (MSB)
D11
D10
D9
D8
ANALOG PINS
V
REFT2345
Top Reference Voltage for DACs 2, 3, 4 and 5
V
REFB2345
Bottom Reference Voltage for DACs 2, 3, 4 and 5
WR
V
CC
GND
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
V
REFB67
RGND
01
RGND
23
RGND
45
RGND
67
V
OUT0–7
V
CC
V
DD
V
SS
GND
PIN FUNCTIONS
Name
CS
WR
Function
Chip Select (Active Low)
Level Triggered Write Input (Active Low). Used in
conjunction with
CS
to write data to the SPT5420
input data latches. Data is latched into selected
input data latch on the rising edge of
WR
.
DIGITAL CONTROL PINS
POWER SUPPLY PINS
ORDERING INFORMATION
PART NUMBER
SPT5420SIM
TEMPERATURE RANGE
–40 to +85 °C
PACKAGE
44L MQFP
SPT5420
8
6/26/01
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
