DATA SHEET
SPT5240
Electrical Specifications
(
T
A
= 25°C, AV
DD
= 3.3V, DV
DD
= 3.3V,
ƒ
OUT
= 1.27MHz,
ƒ
CLK
= 400MHz, Clock Duty Cycle = 50%,
I
OUT
= 20mA, R
L
= 50
Ω
; unless otherwise noted)
Parameter
DC Performance
Resolution
Differential Linearity Error (DLE)
Integral Linearity Error (ILE)
Offset Error
Full Scale Error
Gain Error
Maximum Full Scale Output Current
Output Compliance Voltage
Output Impedance
Gain Error Tempco
AC Performance
Maximum Clock Rate
Glitch Energy
Settling Time (t
settling
)
Output Rise Time
Output Fall Time
Output Delay Time (t
D
)
Spurious Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Digital and Clock Data Input
V
IH
Minimum
V
IL
Maximum
Logic “1” Current
Logic “0” Current
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Clock Feedthrough
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing
actually performed during production and Quality Assurance inspection.
LEVEL
I
IV
V
TEST PROCEDURE
100% production tested at the specified temperature.
Parameter is guaranteed by design or characterization data.
Parameter is a typical value for information purposes only.
See Figure 1
See Figure 1
V
V
I
I
V
V
V
-10
-10
1
1
-29
2
1
+10
+10
V
V
µ
A
µ
A
ns
ns
dBFS
See Figure 1
Major code transition
See Figure 1, major code trans.
IV
V
V
V
V
V
V
V
400
7
7.5
1.3
1.5
1.8
58
-55
MHz
pV-s
ns
ns
ns
ns
dBc
dBc
Full-scale output
DC at IO
N
DC at IO
N
DC at both outputs
DC at both outputs
DC at both outputs
I
I
I
I
I
V
V
V
V
-1
-4
-.005
-15
-15
30
1.5
250
±300
±1.34
10
2
4
+15
+15
Bits
LSB
LSB
%FS
%FS
mA
V
k
Ω
ppm
FS/°C
Conditions
Test Level
Min
Typ
Max Units
+.005 %FS
2
REV. 1 June 2003
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
