欢迎访问ic37.com |
会员登录 免费注册
发布采购

SPT1175ACS 参数 Datasheet PDF下载

SPT1175ACS图片预览
型号: SPT1175ACS
PDF下载: 下载PDF文件 查看货源
内容描述: 8位, 20 MSPS的CMOS A / D转换器 [8-BIT, 20 MSPS CMOS A/D CONVERTER]
分类和应用: 转换器
文件页数/大小: 8 页 / 163 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
 浏览型号SPT1175ACS的Datasheet PDF文件第1页浏览型号SPT1175ACS的Datasheet PDF文件第3页浏览型号SPT1175ACS的Datasheet PDF文件第4页浏览型号SPT1175ACS的Datasheet PDF文件第5页浏览型号SPT1175ACS的Datasheet PDF文件第6页浏览型号SPT1175ACS的Datasheet PDF文件第7页浏览型号SPT1175ACS的Datasheet PDF文件第8页  
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
(1)
25
°
C
Supply Voltages
V
DD
........................................................... -0.5 to +7.0 V
Input Voltages
Analog Input .............................................. AGND to V
DD
Reference Input Voltage ........................... AGND to V
DD
ESD Susceptibility
(2) .................................................
±1,500
V
Temperature
Operating Temperature ................................. 0 to +70
°C
Junction Temperature ........................................... 175
°C
Lead Temperature, (soldering 10 seconds) .......... 300
°C
Storage Temperature ................................ -55 to +125
°C
Notes:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
2. 100 pF discharged through a 1.5 kΩ resistor (human body model).
ELECTRICAL SPECIFICATIONS
T
A
= +25
°C,
AV
DD
=DV
DD
=+5.0 V, AGND=DGND=0.0 V, V
RB
=+0.6 V and V
RT
=+2.6 V, unless otherwise specified.
PARAMETERS
Resolution
DC Accuracy (+25
°C)
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Analog Input
Input Voltage Range
Input Bias Current
Input Resistance
Input Capacitance
Input Bandwidth
Reference Input
Reference Ladder Resistance
Reference Current
Reference Input Voltage
Internal Bias
TEST
CONDITIONS
TEST
LEVEL
MIN
8
SPT1175
TYP
MAX
UNITS
Bits
I
I
I
I
I
VI
V
V
I
I
IV
IV
I
I
V
RB
100
12
200
5.0
0
-
0.55
1.9
±0.8
±0.6
Guaranteed
±1.2
±1.0
LSB
LSB
V
RT
±5.0
200
15
V
µA
kΩ
pF
MHz
mA
V
V
V
V
V
RB
V
RT
V
RB
V
RT
-V
RB
Short V
RT
and V
RTS
Short V
RB
and V
RBS
300
6.7
0.6
2.6
0.60
2.0
400
10.0
-
2.8
0.65
2.1
Offset Voltage Error
Top
Bottom
Timing Characteristics
Maximum Conversion Rate
Output Data Delay (td)
Output Data Delay
(Tdish, Tdisl)
Data Valid Time
(Teneh, Tenel)
Sampling Time Offset
1 MHz Input Sine Wave
(High Z)
Tri-State Circuit
I
I
I
IV
IV
IV
IV
-18
0
20
-25
10
30
18
-68
40
mV
mV
MSPS
ns
ns
ns
ns
30
100
100
5
10
NOTE: It is strongly recommended that all of the supply pins (AV
DD
, DV
DD
) be powered from the same source.
SPT1175
2
6/24/97